參數(shù)資料
型號： XRT86VL38_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 36/66頁
文件大?。?/td> 425K
代理商： XRT86VL38_1
XRT86VL38
33
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
RxCHCLK0
RxCHCLK1
RxCHCLK2
RxCHCLK3
RxCHCLK4
RxCHCLK5
RxCHCLK6
RxCHCLK7
A8
A14
A24
F25
AB24
AE21
AE11
AF5
E10
E15
B20
G19
U18
AB19
AA8
Y5
O
8
Receive Channel Clock Output (RxCHCLKn):
The exact function of this pin depends on whether or not
the receive framer enables the receive fractional/signaling
interface to output fractional data, as described below.
If receive fractional/signaling interface is disabled:
This pin indicates the boundary of each time slot of an
inbound DS1/E1 frame. In T1 mode, each of these output
pins is a 192kHz clock which pulses "High" during the
LSB of each 24 time slots. In E1 mode, each of these out-
put pins is a 256kHz clock which pulses "High" during the
LSB of each 32 time slots. System Equipment can use
this clock signal to sample the RxCHN0 through RxCHN4
time slot identifier pins to determine which time slot is
being output.
If receive fractional/signaling interface is enabled:
RxCHCLKn is the fractional interface clock which either
outputs a clock signal for the time slot that has been con-
figured to output fractional data, or outputs an enable sig-
nal for the fractional time slot so that fractional data can
be clocked out of the device using the RxSERCLK pin.
N
OTE
:
Receive fractional interface can be enabled by
programming to bit 4 - RxFr1544/RxFr2048 bit
from register 0xn122 to ‘1’.
RECEIVE SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
420 P
KG
B
ALL
#
484 P
KG
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
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