參數(shù)資料
型號: XRT86VL32IB
廠商: Exar Corporation
文件頁數(shù): 153/155頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 2CH 225BG
標準包裝: 84
控制器類型: T1/E1/J1 調幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應商設備封裝: 225-BGA(19x19)
包裝: 托盤
XRT86VL32
92
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2
Rx OOF
State
Change
RUR/
WC
0
Change in Receive Out of Frame Defect Condition Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in Receive
Out of Frame Defect Condition” interrupt has occurred since the last read of this
register.
Out of Frame defect condition is declared when “TOLR” out of “RANG” errors in
the framing bit pattern is detected. (Register 0xn10B)
If this interrupt is enabled, then the Receive T1 Framer block will generate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Out of Frame defect
condition.
2. Whenever the Receive T1 Framer block clears the Out of Frame defect
condition
0 = Indicates that the “Change in Receive Out of Frame defect condition” interrupt
has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Out of Frame defect condition” interrupt
has occurred since the last read of this register
1
RxAIS State
Change
RUR/
WC
0
Change in Receive AIS Condition Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in Receive
AIS Condition” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the AIS condition.
2. Whenever the Receive T1 Framer block clears the AIS condition
0 = Indicates that the “Change in Receive AIS condition” interrupt has not
occurred since the last read of this register
1 = Indicates that the “Change in Receive AIS condition” interrupt has occurred
since the last read of this register
0
RxYEL State
Change
RUR/
WC
0
Change in Receive Yellow Alarm Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in Receive
Yellow Alarm Condition” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Yellow Alarm
condition.
2. Whenever the Receive T1 Framer block clears the Yellow Alarm condition
0 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt has
not occurred since the last read of this register
1 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt has
occurred since the last read of this register
TABLE 80: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR)
HEX ADDRESS: 0XnB02
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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