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參數(shù)資料
型號: XRT83SL38IB
廠商: Exar Corporation
文件頁數(shù): 83/88頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
標準包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83SL38
82
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 27 and
Figure 29 is described in Table 51.
FIGURE 27. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
TABLE 51: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
t0
Valid Address to CS Falling Edge
0
-
ns
t1
CS Falling Edge to RD Assert
20
-
ns
t2
RD Assert to RDY Assert
-
135
ns
NA
RD Pulse Width (t2)
135
-
ns
t3
CS Falling Edge to WR Assert
20
-
ns
t4
WR Assert to RDY Assert
-
135
ns
NA
WR Pulse Width (t2)
135
-
ns
t5
CS Falling Edge to AS Falling Edge
0
-
ns
Reset pulse width - both Motorola and Intel Operations (see
t9
Reset pulse width
10
s
AD D R[6:0]
DA TA[7:0]
RD_DS
WR _R/W
RDY _DTAC K
V alid Data for R eadbac k
D ata Available to W rite Into the LIU
R EAD OPER ATIO N
W RITE OPER ATIO N
t
0
t
0
t
1
t
3
t
2
t
4
Valid Address
V alid Addres s
t
5
t
5
ALE_AS
CS
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