參數(shù)資料
型號: XRT83SL30IV-F
廠商: Exar Corporation
文件頁數(shù): 5/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 SGL 64TQFP
標準包裝: 160
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 1/1
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 托盤
XRT83SL30
10
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MCLKT1
14
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
NOTES:
1.
See MCLKE1 description for further explanation for the usage of
this pin.
2.
Internally pulled “Low” with a 50k
resistor.
MCLKOUT
16
O
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based on the mode of operation.
CLKSEL2
CLKSEL1
CLKSEL0
17
18
19
I
Clock Select input for Master Clock Synthesizer pin 2
Clock Select input for Master Clock Synthesizer pin 1
Clock Select input for Master Clock Synthesizer pin 0
In Hardware Mode, CLKSEL[2:0] are input signals to a programmable fre-
quency synthesizer that can be used to generate a master clock from an
external accurate clock source according to the following table. The
MCLKRATE control signal is generated from the state of EQC[4:0] inputs.
See
Table 5 for description of Transmit Equalizer Control bits.
In Host Mode, the state of these pins are ignored and the master frequency
PLL is controlled by the corresponding interface bits.
NOTE: Internally pulled "Low" with a 50k
resistor.
CLOCK SYNTHESIZER
SIGNAL NAME
PIN #TYPE
DESCRIPTION
2048
1544
MCLKE1
(kHz)
8
16
56
8
56
64
128
256
128
2048
1544
MCLKT1
(kHz)
1544
X
1544
X
2048
1544
2048
CLKOUT
(KHz)
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
1
CLKSEL0
0
1
0
1
0
1
0
CLKSEL1
1
0
1
0
1
0
CLKSEL2
0
1
0
1
0
1
0
1544
2048
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
1
0
1
0
1
0
1
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