
XRT83SL216
5
REV. 1.0.0
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RLOS15
RLOS14
RLOS13
RLOS12
RLOS11
RLOS10
RLOS9
RLOS8
RLOS7
RLOS6
RLOS5
RLOS4
RLOS3
RLOS2
RLOS1
RLOS0
B10
D11
F10
B12
T12
T11
M10
R10
U8
R7
M8
T6
B6
B7
F8
C8
O
Receive Loss of Signal
When a receive loss of signal occurs, the RLOS pin will go "High" for a mini-
mum of one RCLK cycle. RLOS will remain "High" until the loss of signal con-
dition clears. See the Receive Loss of Signal section of this datasheet for
more details.
RCLK15
RCLK14
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
A10
A11
E10
A12
U12
U11
N10
P10
T8
P7
N8
U6
A6
A7
E8
D8
O
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent, RCLK maintains its timing by using an internal master clock
as its reference. RPOS/RNEG data can be updated on either edge of RCLK
selected by RCLKinv in the appropriate channel register.