參數(shù)資料
型號(hào)： XRT83SH314
廠商： Exar Corporation
英文描述： 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 14-CHANNEL的T1/E1/J1短途線路接口單元
文件頁(yè)數(shù)： 4/101頁(yè)
文件大小： 656K
代理商： XRT83SH314
XRT83SH314
I
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS ..........................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT83SH314................................................................................................................................. 1
FEATURES
.....................................................................................................................................................................1
P
RODUCT
O
RDERING
I
NFORMATION
................................................................................................................................2
P
IN
O
UT
OF
THE
XRT83SH314.....................................................................................................................................3
T
ABLE
OF
C
ONTENTS
............................................................................................................I
PIN DESCRIPTIONS (BY FUNCTION)........................................................................................... 4
M
ICROPROCESSOR
........................................................................................................................................................4
R
ECEIVER
S
ECTION
.......................................................................................................................................................5
T
RANSMITTER
S
ECTION
..................................................................................................................................................8
C
ONTROL
F
UNCTION
....................................................................................................................................................10
C
LOCK
S
ECTION
..........................................................................................................................................................10
JTAG S
ECTION
...........................................................................................................................................................10
P
OWER
AND
G
ROUND
..................................................................................................................................................11
N
O
C
ONNECTS
............................................................................................................................................................13
1.0 CLOCK SYNTHESIZER .......................................................................................................................14
T
ABLE
1: I
NPUT
C
LOCK
S
OURCE
S
ELECT
.............................................................................................................................................. 14
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
C
LOCK
S
YNTHESIZER
................................................................................................... 15
1.1 ALL T1/E1 MODE ........................................................................................................................................... 15
2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................15
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
............................................................................................................ 15
2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 16
2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 16
T
ABLE
2: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
.................................................................................................................................... 16
F
IGURE
4. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.......................................................................................... 16
2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 17
T
ABLE
3: S
ELECTING
THE
V
ALUE
OF
THE
E
XTERNAL
F
IXED
R
ESISTOR
.................................................................................................... 17
F
IGURE
5. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
O
NE
E
XTERNAL
F
IXED
R
ESISTOR
.............................................................................. 17
2.2 CLOCK AND DATA RECOVERY ................................................................................................................... 18
F
IGURE
6. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK..................................................................................................... 18
F
IGURE
7. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK................................................................................................... 18
T
ABLE
4: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG................................................................................................................. 19
2.2.1 RECEIVE SENSITIVITY .............................................................................................................................................. 19
F
IGURE
8. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
.............................................................................................. 19
2.2.2 INTERFERENCE MARGIN ......................................................................................................................................... 20
F
IGURE
9. T
EST
C
ONFIGURATION
FOR
M
EASURING
I
NTERFERENCE
M
ARGIN
........................................................................................... 20
2.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 20
F
IGURE
10. I
NTERRUPT
G
ENERATION
P
ROCESS
B
LOCK
......................................................................................................................... 21
F
IGURE
11. A
NALOG
R
ECEIVE
L
OS
OF
S
IGNAL
FOR
T1/E1/J1................................................................................................................ 22
T
ABLE
5: A
NALOG
RLOS D
ECLARE
/C
LEAR
(T
YPICAL
V
ALUES
)
FOR
T1/E1............................................................................................. 22
2.3 JITTER ATTENUATOR ................................................................................................................................... 23
2.4 HDB3/B8ZS DECODER .................................................................................................................................. 23
2.5 RPOS/RNEG/RCLK ........................................................................................................................................ 24
F
IGURE
12. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
......................................................................................... 24
F
IGURE
13. D
UAL
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
............................................................................................ 24
2.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) ....................................................................................... 24
F
IGURE
14. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
X
MUTE F
UNCTION
................................................................................................... 24
3.0 TRANSMIT PATH LINE INTERFACE ..................................................................................................25
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
......................................................................................................... 25
3.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 25
F
IGURE
16. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK...................................................................................................... 25
F
IGURE
17. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK........................................................................................................ 26
T
ABLE
6: T
IMING
S
PECIFICATIONS
FOR
TCLK/TPOS/TNEG.................................................................................................................. 26
3.2 HDB3/B8ZS ENCODER .................................................................................................................................. 26
T
ABLE
7: E
XAMPLES
OF
HDB3 E
NCODING
............................................................................................................................................ 26
T
ABLE
8: E
XAMPLES
OF
B8ZS E
NCODING
............................................................................................................................................. 27
3.3 JITTER ATTENUATOR ................................................................................................................................... 27
T
ABLE
9: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
........................................................................................... 27
3.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 27
相關(guān)PDF資料
PDF描述
XRT83SH314_0610 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83SH314_0610 制造商:EXAR 制造商全稱:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH314ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 CHT1/E1LIU SH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SH314IB 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83SH314IB-F 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
XRT83SH314IB-SAK 制造商:Exar Corporation 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 制造商:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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