參數(shù)資料
型號(hào)： XRT83SH314_0610
廠商： Exar Corporation
英文描述： 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： 14-CHANNEL的T1/E1/J1短途線路接口單元
文件頁(yè)數(shù)： 5/101頁(yè)
文件大小： 656K
代理商： XRT83SH314_0610
XRT83SH314
II
REV. 1.0.4
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
F
IGURE
18. TAOS (T
RANSMIT
A
LL
O
NES
) ............................................................................................................................................ 27
3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 27
3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 28
F
IGURE
19. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
ATAOS F
UNCTION
..................................................................................................... 28
3.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 28
T
ABLE
10: R
ANDOM
B
IT
S
EQUENCE
P
OLYNOMIALS
................................................................................................................................ 28
3.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28
3.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 29
T
ABLE
11: S
HORT
H
AUL
L
INE
B
UILD
O
UT
.............................................................................................................................................. 29
3.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 29
F
IGURE
20. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
......................................................................................................................... 29
3.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE................................................................................. 30
T
ABLE
12: T
YPICAL
ROM V
ALUES
........................................................................................................................................................ 30
3.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30
3.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 30
F
IGURE
21. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
......................................................................................... 31
4.0 T1/E1 APPLICATIONS ........................................................................................................................32
4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
F
IGURE
22. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
................................................................................................ 32
4.1.2 REMOTE LOOPBACK................................................................................................................................................ 32
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.......................................................................................................... 32
4.1.3 DIGITAL LOOPBACK................................................................................................................................................. 33
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
........................................................................................................... 33
4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
UAL
L
OOPBACK
............................................................................................................... 33
4.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 34
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
AN
84-C
HANNEL
A
PPLICATION
........................................................................................... 34
T
ABLE
13: C
HIP
S
ELECT
A
SSIGNMENTS
................................................................................................................................................ 34
4.3 LINE CARD REDUNDANCY .......................................................................................................................... 35
4.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 35
4.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 35
F
IGURE
27. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
................................................ 35
4.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 36
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
.................................................. 36
4.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
4.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 37
F
IGURE
29. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
............................................................ 37
4.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 38
F
IGURE
30. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
.............................................................. 38
4.4 POWER FAILURE PROTECTION .................................................................................................................. 39
4.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 39
4.6 NON-INTRUSIVE MONITORING .................................................................................................................... 39
F
IGURE
31. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
..................................................................... 39
4.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 40
F
IGURE
32. ATP
TESTING
BLOCK
DIAGRAM
........................................................................................................................................... 40
F
IGURE
33. T
IMING
D
IAGRAM
FOR
ATP T
ESTING
................................................................................................................................. 40
4.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 40
4.7.2 RECEIVER RTIP AND RRING.................................................................................................................................... 41
4.8 XRT83SH314 JITTER CHARACTERISTICS .................................................................................................. 42
4.8.1 JITTER TOLERANCE................................................................................................................................................. 42
F
IGURE
34. T
EST
C
IRCUIT
FOR
DS-1 J
ITTER
T
OLERANCE
...................................................................................................................... 42
F
IGURE
35. GR-499 J
ITTER
T
OLERANCE
M
ASK
.................................................................................................................................... 42
F
IGURE
36. DS-1 J
ITTER
T
OLERANCE
................................................................................................................................................... 43
F
IGURE
37. DS-1 J
ITTER
T
RANSFER
C
URVE
V
ARIABLE
A
MPLITUDE
- T1 JA DISABLE......................................................................... 44
F
IGURE
38. J
ITTER
T
RANSFER
F
UNCTION
V
ARIABLE
A
MPLITUDE
- T1 TX 3H
Z
32
BITS
........................................................................... 45
F
IGURE
39. J
ITTER
T
RANSFER
F
UNCTION
- T1 TX 3H
Z
64
BITS
.............................................................................................................. 46
F
IGURE
40. J
ITTER
T
RANSFER
F
UNCTION
- T1 RX 3H
Z
32
BITS
........................................................................................................... 47
F
IGURE
41. J
ITTER
T
RANSFER
F
UNCTION
- T1 RX 3H
Z
64
BITS
............................................................................................................ 48
F
IGURE
42. T
EST
C
IRCUIT
FOR
E1 J
ITTER
T
OLERANCE
......................................................................................................................... 49
F
IGURE
43. ITU-G.823 J
ITTER
T
OLERANCE
M
ASK
................................................................................................................................ 49
F
IGURE
44. R
EVISION
C: E1 J
ITTER
T
OLERANCE
- 6
DB
CABLE
+ 6
DB
FLAT
LOSS
................................................................................... 50
F
IGURE
45. J
ITTER
T
RANSFER
F
UNCTION
- JA D
ISABLED
...................................................................................................................... 51
F
IGURE
46. J
ITTER
T
RANSFER
F
UNCTION
- E1 TX 10H
Z
32
BITS
.......................................................................................................... 52
F
IGURE
47. J
ITTER
T
RANSFER
F
UNCTION
- E1 TX 10H
Z
64
BITS
.......................................................................................................... 53
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參數(shù)描述
XRT83SH314ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 CHT1/E1LIU SH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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XRT83SH314IB-SAK 制造商:Exar Corporation 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 制造商:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH38 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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