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參數(shù)資料
| 型號： | XRT83D10 |
| 廠商： | Exar Corporation |
| 英文描述： | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| 中文描述： | 單通道DS1/CEPT線路接口單元 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 258K |
| 代理商： | XRT83D10 |
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SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
XRT83D10
REV. 1.0.3
5
CONTROL FUNCTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
2
ICT
I
In Circuit Testing
When this pin is tied "Low" all output pins are forced to high-impedance state
for in-circuit testing.
N
OTE
:
Internally pulled up.
16
ExCLK
I
External Clock Input:
DS1 (1.544 MHz ± 130 ppm) or CEPT E1 (2.048 MHz ± 80 ppm) clock signal is
provided. ExCLK must be an independent clock to guarantee device perfor-
mance for all specifications. This clock must be continuously active (ungapped
or unswitched) and void of jitter for the device to operate properly.
11
TAOS
I
Transmit All Ones:
With this pin tied "High", an AMI encoded all "1’s" signal sent to the transmit
output using ExCLK as the timing reference. A remote loop back has higher
priority over TAOS request.
N
OTE
:
Internally pulled down.
9
LOOPB
I
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
N
OTE
:
Internally Pulled down.
10
LOOPA
I
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
N
OTE
:
Internally Pulled down.
13
FOFS
O
FIFO Overflow Signal:
This pin is set "High" if the phase jitter of the incoming signal exceeds the toler-
ance of the jitter attenuator’s buffer. This may result in loss of data and Jitter
Attenuator is no longer attenuating jitter.
POWER AND GROUND
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
3
AVDD
****
Analog Supply: 5V ± 5% or 3.3V ± 5%
4
AGND
****
Analog GND.
24
DVDD
****
Digital Supply: 5V ± 5% or 3.3V ± 5%
26
DGND
****
Digital GND
LOOPA
0
0
Loopback Mode
Normal Operation
Digital
LOOPB
0
1
1
1
Remote
Local
0
1
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PDF描述 |
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| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83L314 | 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT |
| XRT83L314IB | 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT |
| XRT83L34 | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L34IV | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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