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XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
5
FIGURE 3. LVDS OUTPUT WAVEFORMS AND TEST CIRCUITS
1.0
CALIBRATION
TABLE 1: FREQUENCY SELECTION TABLE
FS0
PIN 10
FS1
PIN 9
CRYSTAL OR CLOCK
FREQUENCY
INTERNAL
CAPACITOR
MULTIPLY
RATIO
OUTPUT
DIVIDE
OUTPUT
FREQUENCY
1
78.0 MHz Clock
NA
8x
1
624 MHz
0
1
39.0 MHz
12 pF
16x
1
624 MHz
1
0
19.5 MHz
20 pF
32x
1
624 MHz
0
19.5 MHz
20 pF
32x
2
312 MHz
NOTES:
1. Use Parallel Fundamental mode crystal
2. FS0 has an internal 50K
pull-up resistor to VDD
3. FS1 has an internal 50K
pull-down resistor to GND
TABLE 2: POWER-DOWN AND OUTPUT TRI-STATE SELECTION TABLE
PD
PIN 8
OE
PIN 7
STATUS
NOTES:
1
X
Outputs tri-stated and chip Powered-down
1. “X" = Don't care
2. PD and OE have an internal 50K
pull-down resis-
tor to ground.
0
1
Output tri-stated
V
OUT
C
L =5 pF
C
L =5 pF
R
L = 100
OUTP
OUTN
V
OUT
V
CM
OUTP
OUTN
50
50
LDVS Levels Test Circuit
LDVS Switching Test Circuit
OUTP
OUTN
T
R
T
F
80%
20%
80%
20%
0V
VCM (Differential)
LDVS Transition Time Waveform
0V (Differential)
VOUT
50%
t
skew