參數(shù)資料
型號(hào)： XRT8001IP
廠商： EXAR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： WAN Clock for T1 and E1 Systems
中文描述： 8001 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP18
封裝： 0.300 INCH, PLASTIC, DIP-18
文件頁(yè)數(shù)： 36/48頁(yè)
文件大?。?/td> 1054K
代理商： XRT8001IP
XRT8001
36
Rev. 1.01
7.1 Synthesizing an “M x 2.048MHz” clock signal,
such that “M” can take on the value of “1”, “2”, “4”,
or “8” with a clock signal of 2.048MHz
Figure 21 presents a possible approach that can be
used. In this example, the user takes the 2.048MHz
clock signal, and runs it through an external “Divide-
by-32” counter (which is realized with two
74AHCT193). This “Divide-by-32” counter generates
a 64kHz clock signal, which is applied to the “FIN”
input pin of the XRT8001.
SeriSerial_Clock
64kHz Clock Signal
Clear_Counter
2.048MHz_CLOCK
U1
XRT8001
3
18
1
16
17
8
6
13
11
FIN
SCLK
CS
MSB
CLK1
CLK2
LOCKDET
XSerial_Data_In
M x 2.048MHz_CLOCK
WAN_CLOCK_PLL_LOCK_STATUS
U2
74AHCT193
15
1
10
9
5
4
11
14
3
2
6
7
12
13
A
B
C
D
UP
DN
QA
QB
QC
QD
CO
BO
U3
74AHCT193
15
1
10
9
5
4
11
14
3
2
6
7
12
13
A
B
C
D
UP
DN
CLR
QA
QB
QC
QD
CO
BO
R1
1K
1
2
M x 2.048MHz_CLOCK
+5V
Figure 21: Circuit that inputs a 2.048MHz clock and generates a “M” x 2.048MHz clock
If the user configures the XRT8001 WAN Clock to
operate in the “
High Speed – Reverse
” Mode, then
it will accepts a 64kHz clock signal (via the FIN
input) and generates an “M x 2.048MHz” clock
signal via both the CLK1 and CLK2 outputs.
NOTES:
1.
value “1”, “2”, “4” or “8”.
2.
The steps required to configure the XRT8001 into the
“High Speed – Reverse” Mode are presented below.
In this configuration, “M” can be configured to be of
7.2 Configuring the XRT8001 WAN Clock to operate
in the “High Speed – Reverse” Mode.
The following is a “six-step” procedure to configure the
XRT8001 WAN Clock into the “High Speed – Reverse”
Mode.
STEP 1
– Configure the XRT8001 to operate in the
“SLAVE” Mode, by pulling the “MSB” input pin (pin 8)
to GND (low).
STEP 2
– Write the binary expression “1101” into bit-
fields D4 through D1, within Command Register, CR0,
as indicated below.
Command Register, CR1 (Address = 0x01)
D4
D3
M4
M3
1
1
D2
M2
0
D1
M1
1
D0
PL2EN
X
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