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Rev. 1.01 Command Register, CR1 (Address = 0x01) D4 D3 D2 D1 D0 M4 M3 M2 M1 PL2EN 0 1 NOTE: In order to synthesize and output a cloc" />

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參數資料

XRT8001

Rev. 1.01

Command Register, CR1 (Address = 0x01)

PL2EN

NOTE: In order to synthesize and output a clock signal via

the “CLK2” output, the user must write a “1” into the “D0

(PL2EN) bit-field within Command Register, CR1, as

illustrated above.

The values within Command Registers CR2 and CR3

are “don’t care”.

STEP 4 – Enable the desired output signals: SYNC,

CLK1, CLK2, and LOCKDET.

This is accomplished by writing a “1” into the corre-

sponding bit-field, within Command Register, CR4, as

illustrated below.

Command Register, CR4 (Address = 0x04)

SYNCEN

CLK1EN CLK2EN LDETDIS2 LDETDIS1

Once the user has executed these four (4) steps, then

the circuitry in Figure 24 is configured to accept a

1.544MHz clock signal (from the T1/E1 LIU) and

synthesize a 1.544MHz clock signal.

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