參數(shù)資料
型號: XRT79L72IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述: ATM NETWORK INTERFACE, PBGA456
封裝: 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456
文件頁數(shù): 30/72頁
文件大小: 441K
代理商: XRT79L72IB
XRT79L72
REV. P1.0.2
PRELIMINARY
2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
xr
27
F1
E22
RxPOOF
_0
RxPOOF
_1
O
O
Receive PLCP Processor Block - PLCP Out of Frame Defect Indicator:
The XRT79L72 device will assert this output pin (e.g., toggle it "high") anytime
(and for the duration that) the Receive PLCP Processor block is currently
declaring the PLCP OOF (Out of Frame) defect condition.
Conversely, the XRT79L72 device will negate this output pin (e.g., toggle it
"low") anytime (and for the duration that) the Receive PLCP Processor block is
NOT declaring the PLCP OOF defect condition.
N
OTE
:
These output pins are only active if the XRT79L72 has been configured
to operate in both the UNI and PLCP Mode.
E3
E21
RxPLOF
_0
RxPLOF
_1
O
O
Receive PLCP Processor Block - PLCP Loss of Frame Defect Indicator
Output
The XRT79L72 device will assert this output pin (e.g., toggle it "high")
anytime (and for the duration that) the Receive PLCP Processor block
is currently declaring the PLCP LOF (Loss of Frame) defect condi-
tion.Conversely, the XRT79L72 device will negate this output pin (e.g.,
toggle it "low") anytime (and for the duration that) the Receive PLCP
Processor block is NOT declaring the PLCP LOF defect condition.
N
OTE
:
These output pins are only active is the XRT79L72 has been configured
to operate in the ATM/PLCP Mode.
J4
F26
RxOHEnable
_0
/
RxHDLCDat
0
_5
RxOHEnable
_1
/
RxHDLCDat
1
_5
O
O
Receive Overhead Data Output Interface - Enable Output/Receive HDLC
Controller Data Bus - Bit 5 output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer Mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOHEnable:
The XRT79L72 will assert these output signals for one RxOHClk period when it
is safe for the local terminal equipment to sample the data on the RxOH output
pins.
High-Speed HDLC Controller Mode - RxHDLCDat_5:
These output pins along with RxHDLCDatn_[4:0], RxHDLCDatn_6 and
RxHDLCDatn_7 functions as the Receive HDLC Controller byte wide output
data bus. The Receive HDLC Controller will output the contents of all HDLC
frames via this output data bus, upon the rising edge of the RxHDLCClk output
signals. Hence, the user's local terminal equipment should be designed/config-
ured to sample this data upon the falling edge of the RxHDLCClk output clock
signals.
J3
E26
RxOH
_0
/
RxHDLCDat
0
_6
RxOH
_1
/
RxHDLCDat
1
_6
O
O
Receive Overhead Data Output Interface - output/Receive HDLC Controller
Data Bus - Bit 6 output:
The function of these output pins depend upon whether the XRT79L72 has
been configured to operate in the Clear-Channel Framer mode or in the High-
Speed HDLC Controller Mode.
Clear-Channel Framer Mode - RxOH:
All overhead bits, which are received via the Receive Section of the XRT79L72
will be output via these output pins, upon the rising edge of RxOHClk.
High-Speed HDLC Controller Mode - RxHDLCDat_6:
These output pins along with RxHDLCDatn_[5:0] and RxHDLCDatn_7 functions
as the Receive HDLC Controller byte wide output data bus. The Receive HDLC
Controller will output the contents of all HDLC frames via this output data bus,
upon the rising edge of the RxHDLCClk output signals. Hence, the user's local
terminal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signals.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
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