參數(shù)資料
型號(hào)： XRT75R12DIB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA420
封裝： 35 X 35 MM, TBGA-420
文件頁(yè)數(shù)： 6/131頁(yè)
文件大?。?/td> 717K
代理商： XRT75R12DIB
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. P1.0.1
PRELIMINARY
IV
FOR DS3 APPLICATIONS ........................................................................................................................... 106
T
ABLE
46: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
R
EQUIREMENT
PER
T
ELCORDIA
GR-253-CORE,
FOR
DS3
APPLICATIONS
...... 106
8.5.1 DS3 DE-MAPPING JITTER....................................................................................................................................... 107
8.5.2 SINGLE POINTER ADJUSTMENT........................................................................................................................... 107
8.5.3 POINTER BURST...................................................................................................................................................... 107
F
IGURE
55. I
LLUSTRATION
OF
S
INGLE
P
OINTER
A
DJUSTMENT
S
CENARIO
.............................................................................................. 107
8.5.4 PHASE TRANSIENTS............................................................................................................................................... 108
F
IGURE
56. I
LLUSTRATION
OF
B
URST
OF
P
OINTER
A
DJUSTMENT
S
CENARIO
......................................................................................... 108
F
IGURE
57. I
LLUSTRATION
OF
"P
HASE
-T
RANSIENT
" P
OINTER
A
DJUSTMENT
S
CENARIO
.......................................................................... 108
8.5.5 87-3 PATTERN.......................................................................................................................................................... 109
8.5.6 87-3 ADD................................................................................................................................................................... 109
F
IGURE
58. A
N
I
LLUSTRATION
OF
THE
87-3 C
ONTINUOUS
P
OINTER
A
DJUSTMENT
P
ATTERN
.................................................................. 109
8.5.7 87-3 CANCEL............................................................................................................................................................ 110
F
IGURE
59. I
LLUSTRATION
OF
THE
87-3 A
DD
P
OINTER
A
DJUSTMENT
P
ATTERN
..................................................................................... 110
F
IGURE
60. I
LLUSTRATION
OF
87-3 C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
.................................................................................... 110
8.5.8 CONTINUOUS PATTERN......................................................................................................................................... 111
8.5.9 CONTINUOUS ADD................................................................................................................................................. 111
F
IGURE
61. I
LLUSTRATION
OF
C
ONTINUOUS
P
ERIODIC
P
OINTER
A
DJUSTMENT
S
CENARIO
.................................................................... 111
8.5.10 CONTINUOUS CANCEL......................................................................................................................................... 112
F
IGURE
62. I
LLUSTRATION
OF
C
ONTINUOUS
-A
DD
P
OINTER
A
DJUSTMENT
S
CENARIO
............................................................................. 112
F
IGURE
63. I
LLUSTRATION
OF
C
ONTINUOUS
-C
ANCEL
P
OINTER
A
DJUSTMENT
S
CENARIO
....................................................................... 112
8.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ................................ 113
8.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION .............................................................................................................................................. 113
8.7.1 INTRINSIC JITTER TEST RESULTS........................................................................................................................ 113
T
ABLE
47: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
T
EST
R
ESULTS
"
FOR
SONET/DS3 A
PPLICATIONS
......................................... 113
8.7.2 WANDER MEASUREMENT TEST RESULTS.......................................................................................................... 114
8.8 DESIGNING WITH THE LIU ......................................................................................................................... 114
8.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRIN-
SIC JITTER AND WANDER REQUIREMENTS........................................................................................................... 114
F
IGURE
64. I
LLUSTRATION
OF
THE
LIU
BEING
CONNECTED
TO
A
M
APPER
IC
FOR
SONET D
E
-S
YNC
A
PPLICATIONS
.............................. 114
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06...................................................................115
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E ..........................................................115
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16...........................................................115
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06...................................................................116
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E ...............................................................116
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16.................................................................116
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- (C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07.................................................116
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F....................................................116
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17....................................................116
8.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR
TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ...................... 117
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07..................................................117
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F..............................................117
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17..............................................117
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07..................................................117
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F.............................................117
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17.............................................117
F
IGURE
65. I
LLUSTRATION
OF
MINOR PATTERN P1......................................................................................................................... 118
F
IGURE
66. I
LLUSTRATION
OF
MINOR PATTERN P2......................................................................................................................... 119
F
IGURE
67. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
MAJOR PATTERN A....................................................... 119
F
IGURE
68. I
LLUSTRATION
OF
MINOR PATTERN P3......................................................................................................................... 120
F
IGURE
69. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
PATTERN B................................................................... 120
8.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS
OF 50MS (PER TELCORDIA GR-253-CORE) .......................................................................................................... 121
F
IGURE
70. I
LLUSTRATION
OF
THE
SUPER PATTERN
WHICH
IS
OUTPUT
VIA
THE
"OC-N
TO
DS3" M
APPER
IC ................................... 121
F
IGURE
71. S
IMPLE
I
LLUSTRATION
OF
THE
LIU
BEING
USED
IN
A
SONET D
E
-S
YNCHRONIZER
" A
PPLICATION
......................................... 121
T
ABLE
48: M
EASURED
APS R
ECOVERY
T
IME
AS
A
FUNCTION
OF
DS3
PPM
OFFSET
............................................................................. 122
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07..................................................122
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F.............................................122
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17.............................................122
8.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END
CUSTOMER’S SITE................................................................................................................................................... 123
相關(guān)PDF資料
PDF描述
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12IB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00IV E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT79L71 1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R12DIB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R12DIB-L 功能描述:LIN 收發(fā)器 Synch RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT75R12ES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R12IB 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*