參數(shù)資料
型號： XRT75R06DIB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： DATACOM, PCM TRANSCEIVER, PBGA217
封裝： 23 X 23 MM, BGA-217
文件頁數(shù)： 98/105頁
文件大小： 591K
代理商： XRT75R06DIB
XRT75R06D
REV. 1.0.0
á
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
93
CROSS-CHECKING OUR DATA
Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses.
The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
This amount to a period of (2160/51.84MHz) = 41,667ns.
In a period of 41, 667ns, the LIU (when configured to operate in the DS3 Mode), will output a total (41,667ns
x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE LIU
Whenever the LIU is configured to operate in a "SONET De-Sync" application, the device will accept a
continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the
corresponding data). The channel within the LIU (which will be configured to operate in the "DS3" Mode) will
output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter Requirements -
per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure 73.
8.8.3
How does the LIU permit the user to comply with the SONET APS Recovery Time
requirements of 50ms (per Telcordia GR-253-CORE)
Telcordia GR-253-CORE, Section 5.3.3.3 mandates that the "APS Completion" (or Recovery) time be 50ms or
less. Many of our customers interpret this particular requirement as follows.
"From the instant that an APS is initiated on a high-speed SONET signal, all lower-speed SONET traffic (which
is being transported via this "high-speed" SONET signal) must be fully restored within 50ms. Similarly, if the
"high-speed" SONET signal is transporting some PDH signals (such as DS1 or DS3, etc.), then those entities
F
IGURE
72. I
LLUSTRATION
OF
THE
SUPER PATTERN
WHICH
IS
OUTPUT
VIA
THE
"OC-N
TO
DS3" M
APPER
IC
F
IGURE
73. S
IMPLE
I
LLUSTRATION
OF
THE
LIU
BEING
USED
IN
A
SONET D
E
-S
YNCHRONIZER
" A
PPLICATION
PATTERN A
PATTERN A
PATTERN B
IC
DS3 to STS-N
Mapper/
Demapper
LIU
STS-N Signal
TPDATA_n input pin
TCLK_n input
De-Mapped (Gapped)
DS3 Data and Clock
相關(guān)PDF資料
PDF描述
XRT75R06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R06IB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12DIB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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XRT75R06ES 功能描述:時鐘合成器/抖動清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R06IB 功能描述:外圍驅(qū)動器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R06IB208 制造商:Exar Corporation 功能描述:Line Interface Unit 51.84Mbps DS3/E3/STS-1 Parallel 217-Pin BGA
XRT75R06IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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