參數(shù)資料
型號： XRT75R06D
廠商： Exar Corporation
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： 六通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù)： 7/105頁
文件大?。?/td> 591K
代理商： XRT75R06D
á
REV. 1.0.0
XRT75R06D
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
IV
8.5.2 Single Pointer Adjustment ................................................................................................................ 79
8.5.3 Pointer Burst ...................................................................................................................................... 79
Figure 57. Illustration of Single Pointer Adjustment Scenario ........................................................................ 79
8.5.4 Phase Transients ............................................................................................................................... 80
Figure 58. Illustration of Burst of Pointer Adjustment Scenario ...................................................................... 80
Figure 59. Illustration of "Phase-Transient" Pointer Adjustment Scenario ..................................................... 80
8.5.5 87-3 Pattern ........................................................................................................................................ 81
8.5.6 87-3 Add .............................................................................................................................................. 81
Figure 60. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ............................................... 81
8.5.7 87-3 Cancel ......................................................................................................................................... 82
Figure 61. Illustration of the 87-3 Add Pointer Adjustment Pattern ................................................................ 82
Figure 62. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................... 82
8.5.8 Continuous Pattern ............................................................................................................................ 83
8.5.9 Continuous Add ................................................................................................................................ 83
Figure 63. Illustration of Continuous Periodic Pointer Adjustment Scenario ................................................. 83
8.5.10 Continuous Cancel .......................................................................................................................... 84
Figure 64. Illustration of Continuous-Add Pointer Adjustment Scenario ......................................................... 84
Figure 65. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................... 84
8.6 A R
EVIEW
OF
THE
DS3 W
ANDER
R
EQUIREMENTS
PER
ANSI T1.105.03
B
-1997. ............................................... 85
8.7 A R
EVIEW
OF
THE
I
NTRINSIC
J
ITTER
AND
W
ANDER
C
APABILITIES
OF
THE
LIU
IN
A
TYPICAL
SYSTEM
APPLICATION
...
85
8.7.1 Intrinsic Jitter Test results ................................................................................................................ 85
T
ABLE
20: S
UMMARY
OF
"C
ATEGORY
I I
NTRINSIC
J
ITTER
T
EST
R
ESULTS
"
FOR
SONET/DS3 A
PPLICATIONS
....... 85
8.7.2 Wander Measurement Test Results ................................................................................................. 86
8.8 D
ESIGNING
WITH
THE
LIU ................................................................................................................................. 86
8.8.1 How to design and configure the LIU to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements ...................................................................................................................................... 86
Figure 66. Illustration of the LIU being connected to a Mapper IC for SONET De-Sync Applications ........... 86
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06 ................................................... 87
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E ........................................... 87
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16 ........................................... 87
C
HANNEL
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
06 ................................................... 88
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0E ................................................ 88
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
16 ................................................. 88
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- (C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 ................................. 88
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F .................................... 88
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17 .................................... 88
8.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU ............................................................... 89
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 .................................. 89
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F .............................. 89
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17 .............................. 89
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 .................................. 89
C
HANNEL
1 A
DDRESS
L
OCATION
= 0
X
0F ............................. 89
C
HANNEL
2 A
DDRESS
L
OCATION
= 0
X
17 ............................. 89
Figure 67. Illustration of MINOR PATTERN P1 .............................................................................................. 90
Figure 68. Illustration of MINOR PATTERN P2 .............................................................................................. 91
Figure 69. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A ................................ 91
Figure 70. Illustration of MINOR PATTERN P3 .............................................................................................. 92
Figure 71. Illustration of Procedure which is used to Synthesize PATTERN B ............................................. 92
8.8.3 How does the LIU permit the user to comply with the SONET APS Recovery Time requirements
of 50ms (per Telcordia GR-253-CORE) ......................................................................................................................... 93
Figure 72. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC .............. 93
Figure 73. Simple Illustration of the LIU being used in a SONET De-Synchronizer" Application ................... 93
T
ABLE
21: M
EASURED
APS R
ECOVERY
T
IME
AS
A
FUNCTION
OF
DS3
PPM
OFFSET
............................................ 94
J
ITTER
A
TTENUATOR
C
ONTROL
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
07 .................................. 94
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R06DES 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R06DIB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6CH E3/DS3/STS1 LIU w/DeSynch RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R06DIB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 6 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R06ES 功能描述:時鐘合成器/抖動清除器 6CH T3/E3/STS1LIU+JA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R06IB 功能描述:外圍驅(qū)動器與原件 - PCI 6CH E3/DS3/STS1 LIU+Jitter Attenuato RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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