參數(shù)資料
型號(hào): XRT75R03IV-F
廠商: Exar Corporation
文件頁(yè)數(shù): 86/92頁(yè)
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
標(biāo)準(zhǔn)包裝: 72
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 托盤
xr
XRT75R03
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REV. 1.0.8
84
9.0
DIAGNOSTIC FEATURES:
9.1
PRBS Generator and Detector:
The XRT75R03 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN_n bit = “1”, the transmitter
will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS
detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go
“Low” to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the
PRBSLS bit will be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for one RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
Figure 25 shows the status of RNEG/LCV pin when the XRT75R03 is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
9.2
LOOPBACKS:
The XRT75R03 offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback modes
are selected via the RLB_n and LLB_n pins. In Host mode, the RLB_n and LLB_n bits n the Channel control
registers select the loopback modes.
9.2.1
ANALOG LOOPBACK:
1
JA in Tx Path Ch_n
R/W
0
Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator
(within Channel_n) to operate in either the Transmit or
Receive path, as described below.
0 - Configures the Jitter Attenuator (within Channel_n) to
operate in the Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to
operate in the Transmit Path.
0
JA0 Ch_n
R/W
0
Jitter Attenuator Configuration Select Input - Bit 0:
Please see the description for Bit 2 (JA1 Ch_n).
FIGURE 26. PRBS MODE
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
RClk
RNEG/LCV
SYNC LOSS
PRBS SYNC
Single Bit Error
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