參數(shù)資料
型號： XRT75L04DIV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP176
封裝： 24 X 24 MM, 1.40 MM HEIGHT, TQFP-176
文件頁數(shù)： 5/98頁
文件大?。?/td> 536K
代理商： XRT75L04DIV
á
REV. 1.0.1
XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2
5.1 AGC/EQUALIZER: .......................................................................................................................................... 30
5.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 30
F
IGURE
17. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
DS3/STS-1...................................................................................................... 30
5.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 31
5.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 31
F
IGURE
18. I
NTERFERENCE
M
ARGIN
T
EST
S
ET
UP
FOR
E3.................................................................................................................... 31
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
................................................................................................................................. 31
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 32
5.4.1 DS3/STS-1 LOS CONDITION:.................................................................................................................................... 32
D
ISABLING
ALOS/DLOS D
ETECTION
:.......................................................................................................................... 32
5.4.2 E3 LOS CONDITION:.................................................................................................................................................. 32
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
REQEN (DS3
AND
STS-1 A
P
-
PLICATIONS
).......................................................................................................................................................................... 32
F
IGURE
19. L
OSS
O
F
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775 ................................................................................................ 33
F
IGURE
20. L
OSS
OF
S
IGNAL
D
EFINITION
FOR
E3
AS
PER
ITU-T G.775................................................................................................. 33
5.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 34
6.0 JITTER: ................................................................................................................................................35
6.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 35
6.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 35
F
IGURE
21. J
ITTER
T
OLERANCE
M
EASUREMENTS
.................................................................................................................................. 35
6.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 36
F
IGURE
22. I
NPUT
J
ITTER
T
OLERANCE
F
OR
DS3/STS-1 ...................................................................................................................... 36
F
IGURE
23. I
NPUT
J
ITTER
T
OLERANCE
FOR
E3 .................................................................................................................................... 36
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 37
6.3 JITTER GENERATION: .................................................................................................................................. 37
6.4 JITTER ATTENUATOR: ................................................................................................................................. 37
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
)......................................................................... 37
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
................................................................................................................... 37
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
........................................................................................................................................... 38
F
IGURE
24. J
ITTER
T
RANSFER
R
EQUIREMENTS
AND
J
ITTER
A
TTENUATOR
P
ERFORMANCE
...................................................................... 38
7.0 SERIAL HOST INTERFACE: ...............................................................................................................39
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
................................................................................................................................................ 39
T
ABLE
15: R
EGISTER
M
AP
AND
B
IT
N
AMES
........................................................................................................................................... 39
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
............................................................................................................................... 40
T
ABLE
17: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
0 R
EGISTERS
.................................................................................................... 41
T
ABLE
18: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
1 R
EGISTERS
.................................................................................................... 41
T
ABLE
19: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
2 R
EGISTERS
.................................................................................................... 42
T
ABLE
20: R
EGISTER
M
AP
AND
B
IT
N
AMES
- C
HANNEL
3 R
EGISTERS
.................................................................................................... 42
T
ABLE
21: R
EGISTER
M
AP
D
ESCRIPTION
.............................................................................................................................................. 43
8.0 DIAGNOSTIC FEATURES: .................................................................................................................47
8.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 47
8.2 LOOPBACKS: ................................................................................................................................................ 48
8.2.1 ANALOG LOOPBACK:............................................................................................................................................... 48
F
IGURE
25. PRBS MODE ................................................................................................................................................................... 48
8.2.2 DIGITAL LOOPBACK:................................................................................................................................................ 49
F
IGURE
26. A
NALOG
L
OOPBACK
........................................................................................................................................................... 49
8.2.3 REMOTE LOOPBACK:............................................................................................................................................... 50
F
IGURE
27. D
IGITAL
L
OOPBACK
............................................................................................................................................................ 50
F
IGURE
28. R
EMOTE
L
OOPBACK
........................................................................................................................................................... 50
8.3 TRANSMIT ALL ONES (TAOS): .................................................................................................................... 51
F
IGURE
29. T
RANSMIT
A
LL
O
NES
(TAOS) ............................................................................................................................................ 51
9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ...............................................................52
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 52
F
IGURE
30. A S
IMPLE
I
LLUSTRATION
OF
A
DS3
SIGNAL
BEING
MAPPED
INTO
AND
TRANSPORTED
OVER
THE
SONET N
ETWORK
............... 53
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 54
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 54
9.2.1.1 A B
RIEF
D
ESCRIPTION
OF
AN
STS-1 F
RAME
......................................................................................................... 54
F
IGURE
31. A S
IMPLE
I
LLUSTRATION
OF
THE
SONET STS-1 F
RAME
..................................................................................................... 55
F
IGURE
32. A S
IMPLE
I
LLUSTRATION
OF
THE
STS-1 F
RAME
S
TRUCTURE
WITH
THE
TOH
AND
THE
E
NVELOPE
C
APACITY
B
YTES
D
ESIGNATED
56
F
IGURE
33. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
................................................................................................. 57
F
IGURE
34. T
HE
B
YTE
-F
ORMAT
OF
THE
TOH
WITHIN
AN
STS-1 F
RAME
................................................................................................. 58
9.2.1.2 M
APPING
DS3
DATA
INTO
AN
STS-1 SPE ............................................................................................................ 59
F
IGURE
35. I
LLUSTRATION
OF
THE
B
YTE
S
TRUCTURE
OF
THE
STS-1 SPE............................................................................................. 59
相關(guān)PDF資料
PDF描述
XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L04IV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75L04DIV-F 功能描述:外圍驅(qū)動器與原件 - PCI 4-Ch DS3, E3, STS-1 RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75L04DIVTR 功能描述:時鐘合成器/抖動清除器 4 CHNL E3/DS3/STS 1 JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04DIVTR-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04ES 功能描述:時鐘合成器/抖動清除器 4CH T3/E3/STS1 LIU+JA 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75L04IV 功能描述:外圍驅(qū)動器與原件 - PCI 4CH E3/DS3/STS1 JITTER ATTENUATOR RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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