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參數(shù)資料
| 型號： | XRT73R12IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA420 |
| 封裝： | 35 X 35 MM, TBGA-420 |
| 文件頁數(shù)： | 67/87頁 |
| 文件大小： | 436K |
| 代理商： | XRT73R12IB |
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PRELIMINARY
XRT73R12
REV. P1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
64
B
IT
N
UMBER
N
AME
T
YPE
D
ESCRIPTION
7, 6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Status
Channel 10 Interrupt Status
Channel 9 Interrupt Status
Channel 8 Interrupt Status
Channel 7 Interrupt Status
Channel 6 Interrupt Status
R/O
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT73R12 has a
pending Channel n-related interrupt that is awaiting service. The
last six channels are serviced through this location and the other six
at address 0x61. These two registers are used by the Host to iden-
tify the source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user’s Interrupt Service routine
should be written such that the Microprocessor will now proceed to
read out the contents of the Source Level Interrupt Status Register -
Channel n (Address Locations = 0xn2) to determine the exact
source of the interrupt request.
N
OTE
:
Once this bit-field is set to "1", it will not be cleared back to
"0" until the user has read out the contents of the Source-
Level Interrupt Status Register bit, that corresponds to the
interrupt request channel.
T
ABLE
24: D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR110 (A
DDRESS
L
OCATION
= 0
X
6E)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Part Number ID Value
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
1
1
1
0
1
1
1
B
IT
N
UMBER
N
AME
T
YPE
D
EFAULT
V
ALUE
D
ESCRIPTION
7 - 0
Part Number ID
Value
R/O
0x77
Part Number ID Value:
This READ-ONLY register contains a unique value for the
XRT73R12. This value will always be 0x77.
T
ABLE
25: C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR111 (A
DDRESS
L
OCATION
= 0
X
6F)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Chip Revision Number Value
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
0
X
X
X
X
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參數(shù)描述 |
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