參數(shù)資料
型號： XRT73R06
廠商： Exar Corporation
英文描述： SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述： 六通道線路接口單元E3/DS3/STS-1
文件頁數(shù)： 5/68頁
文件大?。?/td> 347K
代理商： XRT73R06
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73R06
REV. 1.0.0
2
Figure 18. Receive Path Block Diagram ......................................................................................................... 30
4.1 R
ECEIVE
L
INE
I
NTERFACE
................................................................................................................................ 30
Figure 19. Receive Line InterfaceConnection ................................................................................................ 30
4.2 A
DAPTIVE
G
AIN
C
ONTROL
(AGC) .................................................................................................................... 31
4.3 R
ECEIVE
E
QUALIZER
........................................................................................................................................ 31
Figure 20. ACG/Equalizer Block Diagram ...................................................................................................... 31
4.3.1 Recommendations for Equalizer Settings ....................................................................................... 31
4.4 C
LOCK
AND
D
ATA
R
ECOVERY
.......................................................................................................................... 31
4.4.1 Data/Clock Recovery Mode ............................................................................................................... 31
4.4.2 Training Mode .................................................................................................................................... 31
4.5 LOS (L
OSS
OF
S
IGNAL
) D
ETECTOR
.................................................................................................................. 32
4.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 32
4.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 32
T
ABLE
6: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 32
4.5.3 E3 LOS Condition: ............................................................................................................................. 33
Figure 21. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 33
Figure 22. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 33
4.5.4 Interference Tolerance ...................................................................................................................... 34
Figure 23. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 34
Figure 24. Interference Margin Test Set up for E3. ........................................................................................ 34
T
ABLE
7: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 35
4.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 36
4.6 B3ZS/HDB3 D
ECODER
................................................................................................................................... 36
Figure 25. Receiver Data output and code violation timing ............................................................................ 36
5.0 Jitter .................................................................................................................................................. 37
5.1 J
ITTER
T
OLERANCE
.......................................................................................................................................... 37
5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 37
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 37
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 38
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 38
Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 38
5.2 J
ITTER
T
RANSFER
............................................................................................................................................ 39
T
ABLE
8: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ....................................... 39
T
ABLE
9: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
................................................................................. 39
T
ABLE
10: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 39
5.2.1 Jitter Generation ................................................................................................................................ 40
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 40
6.0 Diagnostic Features ......................................................................................................................... 41
6.1 PRBS G
ENERATOR
AND
D
ETECTOR
................................................................................................................. 41
Figure 30. PRBS MODE ................................................................................................................................. 41
6.2 LOOPBACKS ................................................................................................................................................ 42
6.2.1 ANALOG LOOPBACK ........................................................................................................................ 42
Figure 31. Analog Loopback ........................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 43
6.2.3 REMOTE LOOPBACK ........................................................................................................................ 43
Figure 32. Digital Loopback ............................................................................................................................ 43
Figure 33. Remote Loopback ......................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 44
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 44
7.0 Microprocessor interface Block ..................................................................................................... 46
T
ABLE
11: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
...................................................................... 46
Figure 35. Simplified Block Diagram of the Microprocessor Interface Block .................................................. 46
7.1 T
HE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
S
IGNALS
........................................................................................ 47
T
ABLE
12: XRT73R06 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................ 47
7.2 A
SYNCHRONOUS
AND
S
YNCHRONOUS
D
ESCRIPTION
......................................................................................... 48
T
ABLE
13: A
SYNCHRONOUS
T
IMING
S
PECIFICATIONS
......................................................................................... 49
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