參數(shù)資料
型號(hào)： XRT73LC03AIV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 52/61頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 3CH 120LQFP
標(biāo)準(zhǔn)包裝： 72
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 3/3
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-LQFP（14x20）
包裝： 托盤
XRT73LC03A
54
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.4
figures the Transmitter to sample the TPData and
TNData input pins on the falling edge of TxClk.
Bit D1 - TxLEV_(n) (Transmit Line Build-Out En-
able/Disable Select - Channel(n))
This Read/Write bit-field is used to enable or disable
the Channel(n) Transmit Line Build-Out circuit.
Setting this bit-field "High" disables the Channel(n)
Line Build-Out circuit. In this mode, Channel(n) out-
puts partially-shaped pulses onto the line via the
TTIP_(n) and TRing_(n) output pins.
Setting this bit-field "Low" enables the Channel(n)
Line Build-Out circuit. In this mode, Channel(n) out-
puts shaped pulses onto the line via the TTIP_(n) and
TRing_(n) output pins.
In order to comply with the Isolated DSX-3/STSX-1
Pulse Template Requiremnts per Bellcore GR-499-
CORE or GR-253-CORE:
a. Set this bit-field to "1" if the cable length between
the Cross-Connect and the transmit output of Chan-
nel(n) is greater than 225 feet.
b. Set this bit-field to "0" if the cable length between
the Cross-Connect and the transmit output of Chan-
nel(n) is less than 225 feet.
This bit-field is active only if the XRT73LC03A is con-
figured to operate in the DS3 or SONET STS-1
Modes.
If the cable length is greater than 225 feet, set this bit-
field to "1" in order to increase the amplitude of the
Transmit Output Signal. If the cable length is less
than 225 feet, set this bit-field to "0".
NOTE: This option is only available when the XRT73LC03A
is operating in the DS3 or STS-1 Mode.
5.2.3
Command Register CR2-(n)
The bit-format and default values for Command Reg-
ister CR2-(n) are listed below followed by the function
of each of these bit fields.
Bit D4 - Reserved
Bit D3 - Reserved
Bit D2 - ALOSDIS (Analog LOS Disable - Chan-
nel(n))
This Read/Write bit-field is used to enable or disable
the Channel(n) Analog LOS Detector.
Writing a "0" to this bit-field enables the Analog LOS
Detector. Writing a "1" to this bit-field disables the
Analog LOS Detector.
NOTE: If the Analog LOS Detector is disabled, then the
RLOS input pin is only asserted by the DLOS (Digital LOS
Detector).
Bit D1 - DLOSDIS_(n) (Digital LOS Disable - Chan-
nel(n))
This Read/Write bit-field to used to enable or disable
the Channel(n) Digital LOS Detector .
Writing a "0" to this bit-field enables the Digital LOS
Detector. Writing a "1" to this bit-field disables the
Digital LOS Detector.
NOTE: If the Digital LOS Detector is disabled, then the
RLOS input pin is only asserted by the ALOS (Analog LOS
Detector).
Bit D0 - REQEN_(n) (Receive Equalization Enable
- Channel(n))
This Read/Write bit-field is used to enable or disable
the internal Channel(n) Receive Equalizer.
Writing a "1" to this bit-field enables the Internal
Equalizer. Writing a "0" to this bit-field disables the
Internal Equalizer.
5.2.4
Command Register CR3-(n)
The bit-format and default values for Command Reg-
ister CR3-(n) are listed below followed by the function
of each of these bit fields.
COMMAND REGISTER CR2-(n)
D4
D3
D2
D1
D0
Reserved
ENDECDIS_(n)
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X0
0
COMMAND REGISTER CR3-(n)
D4
D3
D2
D1
D0
SR/DR_(n)
LOSMUT_(n)
RxOFF_(n)
RxClk_(n)INV
Reserved
0
000
0
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