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參數(shù)資料
| 型號： | XRT72L74 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 26/104頁 |
| 文件大?。?/td> | 1301K |
| 代理商： | XRT72L74 |
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XRT72L74
FOUR CHANNEL, DS3 ATM UNI/CLEAR-CHANNEL FRAMER
REV. P1.0.0
á
PRELIMINARY
26
J3
J2
J1
J4
TxOHInd/
TxPFrame_0
TxOHInd/
TxPFrame_1
TxOHInd/
TxPFrame_2
TxOHInd/
TxPFrame_3
O
Transmit Overhead Data Indicator/Transmit PLCP Frame Boundary Indica-
tor—Output:
The exact functionality of this output pin depends upon whether the XRT72L71
Framer IC is operating in the Clear Channel or ATM Uni Mode.
Clear Channel Mode:
In the Clear Channel Mode, this pin serves as the transmit OH Indication for the
external interface. This pin is pulsed for one bit period of DS3 clock to indicate to
the external device that the transmit input interface is going to process OH data at
the rising edge of next clock. When the external interface samples TxOHInd as
“High” With the rising edge of DS3 Clk; it is expected NOT to provide useful pay-
load data bit on TxSer pin. Instead it can provide corresponding OH data bit on
TxSer input. However, in that case the user has to program a register bit to config-
ure XRT72L71 to accept the OH data from the TxSer input. Otherwise, the OH
data will be geaerated internally or be taken from the TxOH pin if TxOHIns is
“High”. This pin is pulsed "High" for one bit period prior to all DS3 OH bit positions.
ATM UNI Mode:
In ATM UNI mode of operation, this pin functions as Transmit PLCP Frame signal
which pulses "High" once for each outbound PLCP frame, when the last nibble is
being routed.
M2
M1
N3
N2
TxSerData/
TxPOH_0
TxSerData/
TxPOH_1
TxSerData/
TxPOH_2
TxSerData/
TxPOH_3
I
Transmit Serial Payload Data Input/Transmit PLCP Frame POH Byte Inser-
tion Serial Input:
The exact functionality of this output pin depends upon whether the XRT72L71
Framer IC is operating in the Clear Channel or ATM Uni Mode.
Clear Channel Mode:
In clear channel mode, this pin can be used by the external interface to provide the
serial input data (payload and OH) that has to be mapped in outgoing DS3 frame.
If user want to insert OH data on TxSer pin then the user should configure the
XRT72L71 accordingly.
ATM UNI Mode:
This input pin becomes active when the user asserts the TxPOHIns input pin.
When this happens the user will be permitted to serially input their own value for
PLCP POH bytes into the “outbound” PLCP frame. This data will be clocked into
the UNI Framer via the TxPOHClk output signal. This UNI will also assert the
TxPOHMSB output pin when it expects the MSB (Most significant bit) of the Z6
Byte (within the PLCP frame).
N1
N4
P3
P2
TxPOHClk_0
TxPOHClk_1
TxPOHClk_2
TxPOHClk_3
O
Transmit PLCP Frame POH Byte Insertion Clock:
This pin, along with the TxPOH and the TxPOHMSB input pins, function as the
“Transmit PLCP Frame POH Byte” serial input port. This output pin functions as a
clock output signal that is used to sample the user’s POH data at the TxPOH input
pin. This output pin is always active, independent of the state of the “TxPOHIns”
pin.
N
OTE
:
This output pin is only active if the XRT72L74 has been configured to oper-
ate in the “ATM UNI” Mode.
L2
L1
L4
M3
TxPOHFrame_0
TxPOHFrame_1
TxPOHFrame_2
TxPOHFrame_3
O
Transmit PLCP Frame Path Overhead Byte Serial Input Port—Beginning of
Frame indicator.
This output pin, along with the TxPOH, TxPOHClk, and TxPOHIns pins comprise
the “Transmit PLCP Frame POH Byte Insertion” serial input port. This particular
pin will pulse “High” when the “Transmit PLCP POH Byte Insertion” serial input
port is expecting the first bit of the Z6 byte at the TxPOH input pin.
N
OTE
:
This output pin is only active if the XRT72L74 has been configured to oper-
ate in the “ATM UNI” Mode.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
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| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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| XRT7300IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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