
XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
á
PRELIMINARY
293
As the Transmit E3 Framer block formulates the out-
bound E3 frames, the contents of the BIP-4 bits are
automatically XORed with the contents of this regis-
ter. The results of this XOR operation is written back
into the corresponding bit-field within the outbound
E3 frame, and is transmitted to the Remote Terminal
Equipment. Therefore, if the user does not wish to
modify any of these bits, then this register must con-
tain all “0’s” (the default value).
N
OTE
:
This register is only active if the XRT72L58 Framer
IC has been configured to insert the BIP-4 nibble into each
outbound E3 frame.
5.2.5
The XRT72L58 Framer IC is a digital device that
takes E3 payload and overhead bit information from
some terminal equipment, processes this data and ul-
timately, multiplexes this information into a series of
outbound E3 frames. However, the XRT72L58 Fram-
er IC lacks the current drive capability to be able to di-
rectly transmit this E3 data stream through some
transformer-coupled coax cable with enough signal
strength for it to be received by the remote receiver.
The Transmit E3 Line Interface Block
Therefore, in order to get around this problem, the
Framer IC requires the use of an LIU (Line Interface
Unit) IC. An LIU is a device that has sufficient drive
capability, along with the necessary pulse-shaping
circuitry to be able to transmit a signal through the
transmission medium in a manner that it can be reli-
ably received by the far-end receiver. Figure 120 pre-
sents a circuit drawing depicting the Framer IC inter-
facing to an LIU (XRT7300 DS3/E3/STS-1 Transmit
LIU).
TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A)
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
Not Used
TxBIP-4 Mask[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
F
IGURE
120. A
PPROACH
TO
I
NTERFACING
THE
XRT72L58 F
RAMER
IC
TO
THE
XRT73L04 DS3/E3/STS-1 LIU
A[11:0]
RxSERIAL_CLK_0
R4
31.6
R7
4.7k
HW_RESET*
0.01uF
R5
270
R6
T2
T3001
1
6
3
4
XRT72L58_CS*
T1
T3001
1
6
3
4
DVDD_0
0.01uF
RD*
WR*
R3
31.6
U2
XRT73L04IV_Ch_0
47
49
34
32
80
79
35
36
61
60
59
41
40
42
66
78
58
73
54
64
65
131
75
52
33
31
69
70
71
72
110
TxAVDD0
TxAGND0
TTIP0
TRING0
RTIP0
RRING0
MTIP0
MRING0
RPOS0
RNEG0/LCV0
RCLK0
TPDATA_0
TNDATA_0
TCLK_0
RxAVDD0
RxDVDD0
RxAGND0
RxDGND0
RLOS_0
TxOFF
LOSTHR_0
TxAVDD0
TxAGND0
CS
SCLK
SDI
SDO
REG_RESET*
LIU_SDI
RxRED_ALARM_0
LIU_RLOL_0
D[7:0]
LIU_CS*
J1
BNC
1
2
XMTR_OFF
0.01uF
0.01uF
ALE
J2
BNC
1
2
0.01uF
TxAVDD_0
R1
37.4
U1
XRT72L58_Ch_0
J1
K4
J2
J3
H2
G1
J4
T25
T24
M24
M25
M26
N23
N24
N25
N26
P26
P23
L26
L25
L24
L23
K25
K24
J26
K23
J25
R24
R23
T23
J24
U26
C15
H3
B12
C9
B9
A9
A8
B8
A7
D9
R25
P24
P25
R26
TxPOS_0
TxNEG_0
TxLineClk_0
ExtLOS_0
RxPOS_0
RxNEG_0
RxLineClk_0
RESET
A0
A1
A2
A3
A4
A5
A6
A7
A8
D0
D1
D2
D3
D4
D5
D6
D7
CS
INT
WR_RW
TxSer_0
MOTO
RxLOS_0
NIBBLEINTF
A9
A10
A11
RxFRAME_0
TxFRAME_0
READY_OUT*
RxAVDD_0
R2
37.4
NOTE: LIU Microprocessor
Interface signals originate
from external glue logic
270
Rx_AIS_Ch_0