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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | XRT7295AEIW |
| 寤犲晢锛� | Exar Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 9/15闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC E3 LINE RECEIVER 20SOJ |
| 妯欐簴鍖呰锛� | 36 |
| 椤炲瀷锛� | 鎺ユ敹鍣� |
| 椹�(q奴)鍕曞櫒/鎺ユ敹鍣ㄦ暩(sh霉)锛� | 0/1 |
| 瑕�(gu墨)绋嬶細 | E3 |
| 闆绘簮闆诲锛� | 5V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-BSOJ |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 20-SOJ |
| 鍖呰锛� | 绠′欢 |
XRT7295AE
3
Rev. 2.0.0
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
GNDA
Analog Ground.
2
R
IN
I
Receive Input. Unbalanced analog receive input
3,6
TMC1-TMC2
I
Test Mode Control 1 and 2. Internal test modes are enabled within the device
by using TMC1 and TMC2. Users must tie these pins to the ground plane.
4,5
LPF-1-LPF-2
I
PLL Filter 1 and 2. An external capacitor (0.1
F +/-20%) is connected
between these pins (See Figure 3).
7
RLOS
O
Receive Loss-of-Signal. This pin is set high on loss of signal at the receive
input.
8
RLOL
O
Receive PLL Loss-of-Lock. This pin is set high on loss of PLL frequency lock.
9
GNDD
Digital Ground for PLL Lock. Ground lead for all circuitry running
synchronously with PLL clock.
10
GNDC
Digital Ground for EXCLK. Ground lead for all circuitry running
synchronously with EXCLK.
11
V
DDD
5V Digital Supply (+/-10%) for PLL Clock. Power for all circuitry running
synchronously with PLL clock.
12
V
DDC
5V Digital Supply (+/-10%) for EXCLK. Power for all circuitry running
synchronously with EXCLK.
13
EXCLK
I
External Reference Clock. A valid E3 (34.368MHz +/-100ppm) clock must be
provided at this input. The duty cycle of EXCLK, referenced to V
DD/2 levels,
must be 40%-60%.
14
RCLK
O
Receive Clock. Recovered clock signal to the terminal equipment.
15
RNDATA
O
Receive Negative Data. Negative pulse data output to the terminal
equipment.
16
RPDATA
O
Receive Positive Data. Positive pulse data output to the terminal equipment.
17
ICT
I
Output In-Circuit Test Control (Active-Low). If ICT is forced low, all digital
output pins (RCLK, RPDATA, RNDATA, RLOS, RLOL) are placed in a high-
impedance state to allow for in-circuit testing.
18
REQB
I
Receive Equalization Bypass. A high on this pin bypasses the internal
equalizer. A low places the equalizer in the data path.
19
LOSTHR
I
Loss-of-Signal Threshold Control. The voltage forced on this pin controls the
input loss-of-signal threshold. Three settings are provided by forcing the GND,
V
DD/2, or VDD at LOSTHR.
20
V
DDA
5V Analog Supply (+/-10%).
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| XRT7295AEIW-F | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI E3 Line Receiver RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| XRT7295AEIWTR | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI E3 Line Receiver RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| XRT7295AEIWTR-F | 鍔熻兘鎻忚堪:澶栧湇椹�(q奴)鍕曞櫒鑸囧師浠� - PCI E3 Line Receiver RoHS:鍚� 鍒堕€犲晢:PLX Technology 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FCBGA-1156 灏佽:Tray |
| XRT7295AT | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DS3/Sonet STS-1 Integrated Line Receiver |
| XRT7295AT_10 | 鍒堕€犲晢:EXAR 鍒堕€犲晢鍏ㄧū:EXAR 鍔熻兘鎻忚堪:DS3 SONET STS1 Integrated Line Receiver |
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