參數(shù)資料
型號: XRT71D04
廠商: Exar Corporation
英文描述: 4-Channel E3/DS3/STS-1 Jitter Attenuator,STS-1 to DS3 Desynchronizer(達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
中文描述: 4通道E3/DS3/STS-1抖動衰減器,STS - 1的到DS3 Desynchronizer(達(dá)到E3/DS3/STS-1振蕩要求的4通道振蕩衰減器)
文件頁數(shù): 8/21頁
文件大小: 223K
代理商: XRT71D04
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. P1.0.2
á
PRELIMINARY
7
49
SDO
O
Serial Data Output:
This pin will serially output the contents of the specified Command Register,
during “Read” Operations. The data, on this pin, will be updated on the falling
edge of the SCLK input signal. This pin will be tri-stated upon completion of
data transfer.
50
DS3/E3_ch2
I
DS3/E3 Select Input - channel 1
:
See description pin 9.
Internal 50 K Ohm pull-down resistor.
51
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
52
NC
I
53
RCLKES
I
Received Clock Edge Select Input:
Hardware Mode
1. When RCLKES = “0”, then RPOS and RNEG are updated on the falling
edge of RCLK
2. When RCLKES = “1”, then RPOS and RNEG are updated on the rising
edge of RCLK
N
OTE
:
This applies to all channels.
Host Mode
Connect this pin to GND when the 71D03 is configured in the Host Mode.
Internal 50 K Ohm pull-down resistor.
54
NC
55
RRNEG1
O
Received Recovered Negative Data (De-Jittered) Output - channel
3:
See description of pin 6
56
RRPOS1
O
Received Recovered Positive Data (De-Jittered) Output - channel
1:
See description of pin 5
57
RRCLK1
O
Received Recovered Output (De-jittered) Clock - channel 1:
See description of pin 4
58
VSS
****
Digital Ground
59
NC
60
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
61
AVSS
****
Analog Ground
62
FL1
O
FIFO Limit - channel 1:
See description of pin 22
63
STS1_ch1
I
SONET STS1 Mode Select - channel 1:
See description of pin 23
64
DS3/E3_ch3
I
DS3/E3 Select Input - channel 1
:
See description pin 9.
Internal 50 K Ohm pull-down resistor.
PIN DESCRIPTION
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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