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參數資料
| 型號： | XRK69772 |
| 廠商： | Exar Corporation |
| 英文描述： | 1:12 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 1:12的LVCMOS PLL時鐘發(fā)生器 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 97K |
| 代理商： | XRK69772 |
XRK69772
PRELIMINARY
8
1:12 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.0
3.0
QSYNC TIMING
XRK69772 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK ) CIRCUITRY
The user can write to the serial input register through the STOP_DATA input by supplying a logic ’0’ start bit
followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the
free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK69772 can
sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any
stop bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by
default, enabled.
F
IGURE
4. QSYNC T
IMING
D
IAGRAM
F
IGURE
5. S
TOP
C
LOCK
C
IRCUIT
P
ROGRAMMING
f
VCO
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
QA
QC
QSYNC
1:1 Mode
2:1 Mode
QA
QC
QSYNC
QA(/4)
QSYNC
3:1 Mode
3:2 Mode
QC(/6)
QC(/2)
QSYNC
QA(/6)
2
8
2
9
3
0
3
1
QA(/6)
QSYNC
QC(/8)
QC(/2)
QSYNC
QA(/8)
4:1 Mode
4:3 Mode
QA(/12)
QSYNC
QC(/2)
6:1 Mode
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
STOP_CLK
STOP_DATA
相關PDF資料 |
PDF描述 |
|---|---|
| XRK69772CR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69772IR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773 | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773CR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773IR | 1:12 LVCMOS PLL CLOCK GENERATOR |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XRK69772CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69772IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
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