φφφφφ2 Aperture Delay 0 2.7ns (default) 0 1 4.7ns 0 1 0 6.7ns 0 1 8.7ns " />
參數(shù)資料
型號: XRD98L59AIGTR
廠商: Exar Corporation
文件頁數(shù): 9/37頁
文件大?。?/td> 0K
描述: IC CCD DIGITIZER 10BIT 28TSSOP
產(chǎn)品變化通告: Obsolescence Notification 15/Apr/2010
標準包裝: 1,500
位數(shù): 10
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.6 V
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 帶卷 (TR)
17
Rev. 2.00
XRD98L59
D4
D3
D2
φφφφφ2 Aperture Delay
0
2.7ns (default)
0
1
4.7ns
0
1
0
6.7ns
0
1
8.7ns
1
0
10.7ns
1
0
1
12.7ns
1
0
14.7ns
1
16.7ns
Table 14. Programmable
φφφφφ2 Delays
D7
D6
D5
φφφφφ1 Aperture Delay
0
3.5ns (default)
0
1
5.5ns
0
1
0
7.5ns
0
1
9.5ns
1
0
11.5ns
1
0
1
13.5ns
1
0
15.5ns
1
17.5ns
Table 13. Programmable
φφφφφ1 Delays
SBLK and SPIX Programmable Aperture Delay
(SDI Address = 0010)
The positioning of
φ1 and φ2 from Figure 10, are opti-
mized by using a programmable aperture delay function.
φ1 and φ2 are delayed internally by the amount specified
in the serial port. SBLK delay (D7:D5) delays the
φ1
clock and SPIX delay (D4:D2) delays the
φ2 clock. The
delay is 2ns per lsb. The aperture delays t
BK and tVD are
added to the programmable aperture delay to determine
final positioning. The tables below include the t
BK and tVD
aperture delays.
The aperture delay of
φ2 also delays the output data bus
DB[9:0]. Digital output data is updated on the falling
edge of
φ2 as shown in Figure 10. Data is valid after t
DL
plus the change in
φ2 aperture delay. For example, if
D[4:2] equals 001b, then data is valid at t
DL + 2ns. (tDL
is shown in Figure 6).
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