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參數(shù)資料
| 型號(hào)： | XRD9827ACU |
| 廠商： | EXAR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | 5.30 MM, SSOP-20 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 264K |
| 代理商： | XRD9827ACU |
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XRD9827
6
Rev. 1.20
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AV
DD
=DV
DD
= 5V, ADCCLK=6MHz, 50% Duty Cycle, T
A
=25
°
C unless otherwise specified.
Symbol
System Specifications (MUX + Buffer + PGA + ADC)
SYS
DNL
System DNL
SYS
LIN
System Linearity
SYS
GE
System Gain Error
IRN
Input Referred Noise
Input Referred Noise
System Timing Specifications
tcklw
ADCCLK Low Pulse Width
tckhw
ADCCLK High Pulse Width
tckpd
ADCCLK Period
tsypw
SYNCH Pulse Width
trars
Rising ADCCLK to rising
SYNCH
tclpw
CLAMP Pulse Width
Write Timing Specifications
tsclkw
SCLK Pulse Width
tdz
LD Low to SCLK High
tds
Input Data Set-up Time
tdh
Input Data Hold Time
tdl
SCLK High to LD High
ADC Digital Output Specifications
tap
Aperture Delay
tdv
Output Data Valid
tsa
SYNCH to ADCCLK
tlat
Latency
tlat
Latency
Digital Input Specifications
V
IH
Input High Voltage
V
IL
Input Low Voltage
I
IH
High Voltage Input Current
I
IL
Low Voltage Input Current
C
IN
Input Capacitance
Parameter
Min.
Typ.
Max.
Unit
Conditions
Note 1
-1.0
±0.5
±6.0
+2.3
LSB
LSB
%
mV
rms
mV
rms
-5.0
+5.0
1.5
0.5
Gain=1
Gain=10
50
70
120
30
0
83
83
166
ns
ns
ns
ns
SYNCH must rise equal to
or after ADCCLK, See Figure 18
Note 2
30
ns
40
20
20
0
50
ns
ns
ns
ns
ns
10
ns
ns
ns
40
15
3ch Pixel Md
Config 00, 11
Config 01, 10
8
6
cycles
pixels
AV
DD
-2.5
V
V
μ
A
μ
A
pF
1
5
5
10
Note 1:
Note 2:
System performance is specified for typical digital system timing specifications.
The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
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