Rev. 3.00 Note : These are the control register settings upon initial power-up. The previous register settings are retained followin" />
參數(shù)資料
型號(hào)： XRD9827ACU-F
廠商： Exar Corporation
文件頁數(shù)： 27/36頁
文件大?。?/td> 0K
描述： IC 12B CCD/CIS SIG PROC 20SSOP
標(biāo)準(zhǔn)包裝： 66
位數(shù)： 12
通道數(shù)： 3
電壓 - 電源，模擬： 3 V ~ 5.5V
電壓 - 電源，數(shù)字： 3 V ~ 5.5 V
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 管件
XRD9827
33
Rev. 3.00
Note :
These are the control register settings upon initial power-up. The previous register settings are retained
following a logic power-down initiated by the power down bit except the signal configuration. When
de-selecting the power down bit (D7 = 0, Normal), the signal configuration (D5 and D0) has to be
reprogrammed.
Function
(Register
S2/S1/S0)
D7
D6
D5
D4
D3
D2
D1
D0
Power-up
State
(Note 1)
Red Gain
G5
G4
G3
G2
G1
G0
X
000000XX
(000)
(MSB)
(LSB)
Red Offset
O7
O6
O5
O4
O3
O2
O1
O0
01000000
(001)
(MSB)
(LSB)
Grn Gain
G5
G4
G3
G2
G1
G0
X
000000XX
(010)
(MSB)
(LSB)
Grn Offset
(011)
O7
O6
O5
O4
O3
O2
O1
O0
01000000
(MSB)
(LSB)
Blu Gain
(100)
G5
G4
G3
G2
G1
G0
X
000000XX
(MSB)
(LSB)
Blu Offset
(101)
O7
O6
O5
O4
O3
O2
O1
O0
01000000
(MSB)
(LSB)
Mode
POWER
DIGITAL
V
RT
INPUTDC
DC/AC
SIGNAL
00000000
(110)
DOWN
RESET
REFERENCE
POLARITY
CONFIGURATION
(V
DCREF)
0: NORMAL
0: NO RESET
0: INTERNAL
0: DC
0: Non-
00: Single-Channel
(V
DCREF=AGND)
Inverted
RED input/gain/offset
1:
1:RESET
1: EXTERNAL
1: AC
(CIS)
POWER
(REGISTERS
(V
DCREF=VDCEXT)
1: Inverted
01: Single-Channel
DOWN
ARE RESET TO
(CCD/CIS)
RED input
POWER-UP
RED/GRN/BLU
STATES)
gain/offset cycle
pixel-by-pixel
10: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode
OUTPUT
OFFSET
INTERNAL CIS
TEST4
TEST3
TEST2
TEST1
00000000
&Test
BUS
DISABLE
DAC
REFERENCE
(111)
CONTROL
RANGE
CIRCUIT
0: 6 MSB +
0:OUTPUTS
0:-200mV to
0:NORMAL
0: TEST4
0: TEST3
0: TEST2
0:NORMAL
6 LSB
ENABLED
+600mV
DISABLED
1: 8 MSB +
1:OUTPUTS
1:-400mV to
1:REFERENCE
1: OUTPUT
1: INPUT
1: TEST1
4 LSB
DISABLED
+400mV
CIRCUIT
OF BUFFER
OF PGA
OF ADC
ENABLED
TIED TO
BLU
VDCEXT
GRN
Control Registers
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