參數(shù)資料
型號(hào): XRD9827ACD
廠商: EXAR CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: 12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO20
封裝: 0.300 INCH, SOIC-20
文件頁(yè)數(shù): 29/32頁(yè)
文件大?。?/td> 264K
代理商: XRD9827ACD
XRD9827
29
Rev. 1.20
Note :
These are the control register settings upon initial power-up. The previous register settings are retained
following
a logic power-down initiated by the power down bit except the signal configuration. When
de-selecting the power down bit (D7 = 0, Normal), the signal configuration (D5 and D0) has to be
reprogrammed.
Function
(Register
S2/S1/S0)
D7
D6
D5
D4
D3
D2
D1
D0
Power-up
State
(Note 1)
Red Gain
(000)
G5
G4
G3
G2
G1
G0
(LSB)
X
X
000000XX
(MSB)
Red Offset
(001)
O7
O6
O5
O4
O3
O2
O1
O0
(LSB)
01000000
(MSB)
Grn Gain
(010)
G5
G4
G3
G2
G1
G0
(LSB)
X
X
000000XX
(MSB)
Grn Offset
(011)
O7
O6
O5
O4
O3
O2
O1
O0
(LSB)
01000000
(MSB)
Blu Gain
(100)
G5
G4
G3
G2
G1
G0
(LSB)
X
X
000000XX
(MSB)
Blu Offset
(101)
O7
O6
O5
O4
O3
O2
O1
O0
(LSB)
01000000
(MSB)
Mode
(110)
POWER
DOWN
DIGITAL
RESET
V
RT
INPUT DC
REFERENCE
(V
DCREF
)
DC/AC
SIGNAL
POLARITY
SIGNAL
00000000
CONFIGURATION
0: NORMAL
0: NO RESET
0: INTERNAL
0: INTERNAL
(V
=AGND)
1: EXTERNAL
(V
DCREF
=V
DCEXT
)
0: DC
0: Non-
Inverted
(CIS)
1: Inverted
(CCD/CIS)
00: Single-Channel
RED input/gain/offset
1:
1:RESET
(REGISTERS
ARE RESET TO
POWER-UP
STATES)
1: EXTERNAL
1: AC
POWER
DOWN
01: Single-Channel
RED input
RED/GRN/BLU
gain/offset cycle
pixel-by-pixel
10: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode
&Test
(111)
OUTPUT
BUS
CONTROL
OUTPUT
DISABLE
OFFSET
DAC
RANGE
INTERNAL CIS
REFERENCE
CIRCUIT
TEST4
TEST3
TEST2
TEST1
00000000
0: 6 MSB +
6 LSB
0:OUTPUTS
ENABLED
0:-200mV to
+600mV
0:NORMAL
0: TEST4
DISABLED
0: TEST3
DISABLED
0: TEST2
DISABLED
0:NORMAL
1: 8 MSB +
4 LSB
1:OUTPUTS
DISABLED
1:-400mV to
+400mV
1:REFERENCE
CIRCUIT
ENABLED
1: OUTPUT
OF BUFFER
TIED TO
BLU
1: OUTPUT
OF PGA
TIED TO
VDCEXT
1: INPUT
OF ADC
TIED TO
GRN
1: TEST1
ENABLED
Control Registers
相關(guān)PDF資料
PDF描述
XRD9827 12-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control(12位線性CIS/CCD傳感信號(hào)處理器(帶串行控制))
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