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參數(shù)資料
| 型號(hào)： | XRD9825EVAL |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 30/33頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XRD9825 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XRD9825
6
Rev. 1.00
ELECTRICAL CHARACTERISTICS (CONT'D)
Test Conditions: AV
DD=DVDD= 5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
System Specifications (MUX + Buffer + PGA + ADC)
Note 1
SYS
DNL
System DNL
-1.0
±0.5
+2.3
LSB
SYS
LIN
System Linearity
±6.0
LSB
SYS
GE
System Gain Error
-5.0
+5.0
%
IRN
Input Referred Noise
1.5
mV
rms
Gain=1
Input Referred Noise
0.5
mV
rms
Gain=10
System Timing Specifications
tcklw
ADCCLK Low Pulse Width
50
83
ns
tckhw
ADCCLK High Pulse Width
70
83
ns
tckpd
ADCCLK Period
120
166
ns
tsypw
SYNCH Pulse Width
30
ns
trars
Rising ADCCLK to rising
0
SYNCH must rise equal to
SYNCH
or after ADCCLK, See Figure 18
tclpw
CLAMP Pulse Width
30
ns
Note 2
Write Timing Specifications
tsclkw
SCLK Pulse Width
40
ns
tdz
LD Low to SCLK High
20
ns
tds
Input Data Set-up Time
20
ns
tdh
Input Data Hold Time
0
ns
tdl
SCLK High to LD High
50
ns
ADC Digital Output Specifications
tap
Aperture Delay
10
ns
tdv
Output Data Valid
40
ns
tsa
SYNCH to ADCCLK
15
ns
3ch Pixel Md
tlat
Latency
8
cycles
Config 00, 11
tlat
Latency
6
pixels
Config 01, 10
Digital Input Specifications
V
IH
Input High Voltage
AV
DD-2.5
V
IL
Input Low Voltage
1
V
I
IH
High Voltage Input Current
5
A
I
IL
Low Voltage Input Current
5
A
C
IN
Input Capacitance
10
pF
Note 1:
System performance is specified for typical digital system timing specifications.
Note 2:
The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.
During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the
correct operating level. Refer to the description in Theory of Operation, CIS Config.
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