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參數(shù)資料
| 型號： | XRD9824ACU |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 10/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 14B CCD/CIS SIG PROC 20SSOP |
| 產(chǎn)品變化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 14 |
| 通道數(shù)： | 3 |
| 電壓 - 電源，模擬： | 3 V ~ 5.5V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 5.5 V |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
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XRD9824
18
Rev. 2.00
Figure 12. Timing Diagram for Figure 11
CCD Configuration (Charge Coupled Device)
Mode 1. AC Coupled
In the CCD configuration of operation, an external
capacitor needs to be chosen according to the equa-
tions below. The typical value for the external capaci-
tor is 100pF. This value should be adjusted according
to the time constant (Tc) needed in a particular appli-
cation. The CLAMP pin has an internal 150 ohm
impedance (R
INT) which is in series with the external
capacitor (C
EXT).
Therefore, Tc =1/R
INTCEXT
If the input to the external capacitor has a load imped-
ance (R
EXT), then
T
c=1/(RINT+REXT)CEXT
When CLAMP (clamp) pin is set high an internal switch
allows one side of the external capacitor to be set to
VRT (Figure 13). This value corresponds to the black
reference of the CCD. When the CLAMP pin is set
back to low, the ADC samples the video signal with
respect to the black reference. The difference between
the black reference and the video signal is the actual
pixel value of the video content. Since this value is
referenced to the top ladder reference voltage of the
ADC a zero input signal would yield a full scale output
code.
Therefore, the output of the conversion is
inverted (internally) to correspond to zero scale output
code.
CIS Rotating Gain and Offset
Line-By-Line (Md 11)
ADCCLK
CIS
SYNCH
GAIN/
OFFSET
LD
Red Pixel Line Scan
Grn Pixel Line Scan
Blu Pixel Line Scan
Red Gain/Offset Cycle
Grn Gain/Offset Cycle
Blu Gain/Offset Cycle
Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11)
tsa
tsypw
Note: Y = Previous State
Tri-State (SYNCH = LO)
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