參數資料
型號: XRD9824ACD-F
廠商: Exar Corporation
文件頁數: 20/32頁
文件大?。?/td> 0K
描述: IC 14B CCD/CIS SIG PROC 20SOIC
標準包裝: 37
位數: 14
通道數: 3
電壓 - 電源,模擬: 3 V ~ 5.5V
電壓 - 電源,數字: 3 V ~ 5.5 V
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC W
包裝: 管件
XRD9824
27
Rev. 2.00
Serial Load Control Registers
The serial load registers are controlled by a three wire
serial interface through the bi-directional parallel port
to reduce the pin count of this device. When SYNCH
is set to high, the output bus is tri-stated and the serial
interface is activated. DB7/LD, DB5/SCLK and DB6/
SDATA are the three input signals that control this
process. The DB7/LD signal is set low to initiate the
loading of the internal registers.
There are internal registers that are accessed via an
11-bit data string. Data is shifted in on the rising edge
of SCLK and loaded to the registers on the rising edge
of LD.
The data on pin
DB6/SDATA is latched
automatically after eleven DB5/SCLKs have been
counted. If eleven clocks are not present on DB5/
SCLK before the DB7/LD signal returns high, no data
will be loaded into the internal registers. If more than
11 clocks are present on DB5/SCLK, the additional
clocks will be ignored. The data corresponding to the
first eleven DB5/SCLKs will be loaded only.
The first three MSBs choose which internal register will
be selected. The remaining 8 LSBs contain the data
needed for programming the internal register for a
particular configuration.
Power-Up State of the Internal Registers
The control register settings upon initial power-up are
for CIS, DC Coupled configuration (VRT is set to
internal, Input DC Reference=AGND and the input to
the ADC is selected through the RED channel). Gain
is unity and Offset is set to zero. The test modes are
disabled in the power-up state.
DB6/SDATA
DB5/SCLK
SYNCH
S 2
S 1
S 0
D7
D2
D1
D0
DB7/LD
tdl
tdz
tsclkw
tds tdh
Figure 21. Write Timing
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