參數(shù)資料
型號: XRD9818ACGTR
廠商: Exar Corporation
文件頁數(shù): 4/28頁
文件大?。?/td> 0K
描述: IC 16B CCD/CIS SIG PROC 28TSSOP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 1,500
位數(shù): 16
通道數(shù): 3
功率(瓦特): 325mW
電壓 - 電源,模擬: 3 V ~ 3.6 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 帶卷 (TR)
XRD9818
xr
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
12
3.2
Offset Registers
There are three Offset registers for individual control of the offsets applied to the RED, GREEN, and BLUE
channels. There are separate course and fine controls to set the desired offset compensation for each channel.
Bits D9 and D8 set the course offset from -100mV to +200mV in 100mV increments.
Bits D7:D0 set the fine
offset range from -180mV to +180mV in 1.4mV increments. The polarity of the offset correction is defined as
positive for the normal direction in which offsets occur in an imager, see Figure 11. Please see “Section 4.2,
Programmable Offset Adjust” on page 19 for a description of the XRD9818’s offset correction circuitry.
* Power-on default value
3.3
Mode Registers
There are two mode registers that control the configuration and operation of the XRD9818. The Mode 1
register controls the configuration of input mux mode, gain range, Line Clamp enable, CCD or CIS select, byte
or nibble data output mode and clamp level select.
The Mode 2 register controls the power down, output
enable and polarities of the input timing signals.
* Power-on default value
CH[2:0] - Input Mux/Channel select. Selects between 3-CH (RGB), 1-CH RED, 1-CH GRN,
1-CH BLU, 2-CH (RG), 2-CH (GR), 2-CH (GB) or 2-CH (BR) input mux modes.
GS - Gain Range Select. Gain range 1x to 5x for 3V input signals, range 1.5x to 7.5x for 2V signals.
LC- Line Clamp enable. Gates clamping function with the timing signal LCLMP.
CCDEN - CCD enable. Defines operation for a CCD or CIS imager input.
B/N - Byte or Nibble output mode. Defines 8bit (byte) or 4bit (nibble) data output format.
C/R[2:0] - Clamp/Reference Select. The setting determines the clamp/reference voltage applied
to the CMN- input. The settings 2.0V through VDD are intended for use in CCD applications.
The 0V, 1.25V or "high Z" settings are intended for use for CIS applications. If "high Z"
is selected an external source can be applied to CMN- for the reference. For a description
of the C/R DAC please See “Section 4.1.2, Clamp/Reference (C/R) DAC” on page 17.
OFFSET REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COx[1]
COx[0]
FOx[7]
FOx[6]
FOx[5]
FOx[4]
FOx[3]
FOx[2]
FOx[1]
FOx[0]
Course offset
control
00*
→ 0mV
01
→ -100mV
10
→ 100mV
11
→ 200mV
Fine offset control
01111111
→ 150mV
00000000*
→ 0mV
10000000
→ 0mV
11111111
→ -150mV
MODE 1 REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CH[2]
CH[1]
CH[0]
GS
LC
CCDEN
B/N
C/R[2]
C/R[1]
C/R[0]
000*
→ 3CH (RGB)
001
→ RED channel
010
→ GRN channel
011
→ BLU channel
100
→ 2CH (RG)
101
→ 2CH (GR)
110
→ 2CH (GB)
111
→ 2CH (BR)
0*
→ 1x to 5x
1
→ 1.5x to 7.5x
0*
→ Line Clamp
Off
1
→ Line Clamp
On
0*
→ CCD
1
→ CIS
0
→ byte output
mode
1*
→ nibble out-
put mode
000
→ high Z
001
→ 0V
010
→ 1.25V
011
→ 2.0V
100
→ 2.6V
101
→ 2.8V
110*
→3.0V
111
→ VDD
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