參數(shù)資料
型號(hào)： XRD9818ACG
廠商： EXAR CORP
元件分類： 消費(fèi)家電
英文描述： 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： 4.40 MM, TSSOP-28
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 496K
代理商： XRD9818ACG
xr
XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
13
* Power-on default lt value
PD
- Power Down. Does not affect the internal register settings but does power down the entire part
excluding the serial interface. There will be some power up settling time required to
reestablish the ADC reference, CAPP and CAPN, voltages.
OE
- Output Enable. Tristate control for the output data bus.
L
POL
- LCLMP input polarity select.
(Noninverting pol
active high, inverted pol
active low)
ADC
POL
- ADCLK polarity select.
(Noninverting pol
begins high, inverted pol
begins low)
B
POL
- BSAMP polarity select.
(Noninverting pol
active high, inverted pol
active low)
V
POL
- VSAMP polarity select.
(Noninverting pol
active high, inverted pol
active low)
3.4
The BSAMP Delay register controls the internal delays added to the leading and the trailing edges of the
BSAMP timing signal. The width and position of the BSAMP pulse can be adjusted through the leading and
trailing edge delay settings. This is useful to match the sampling requirements of the incoming CCD waveform.
BSAMP Delay Register
* Power-on default value
BL[4:0]
- Sets the amount of delay added to the leading edge of BSAMP.
BT[4:0]
- Sets the amount of delay added to the trailing edge of BSAMP.
MODE 2 REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PD
OE
N/A
N/A
N/A
N/A
L
POL
ADC
POL
B
POL
V
POL
0*
→
Normal Opera-
tion
1
→
PWR Down
0*
→
Normal Oper-
ation
1
→
Data bus
tri-stated
Not
used
Not
used
Not
used
Not
used
0*
→
Non-
Inverted
1
→
Inverted
0*
→
Non-
Inverted
1
→
Inverted
0*
→
Non-
Inverted
1
→
Inverted
0*
→
Non-
Inverted
1
→
Inverted
BSAMP DELAY REGISTER SETTINGS
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BL[4]
BL[3]
BL[2]
BL[1]
BL[0]
BT[4]
BT[3]
BT[2]
BT[1]
BT[0]
BSAMP Leading edge delay
00000*
→
0ns
00001
→
1ns
…
11110
→
30ns
11111
→
31ns
BSAMP Trailing edge delay
00000*
→
0ns
00001
→
1ns
…
11110
→
30ns
11111
→
31ns
相關(guān)PDF資料
PDF描述
XRD9822 3-Channel, 10/12-Bit Linear CCd and CIS Sensor signal Processors
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XRD9824ACD 14-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control
XRD9825 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control
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