參數(shù)資料
型號: XRD9818
廠商: Exar Corporation
英文描述: 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
中文描述: 3通道16位線陣CCD /獨聯(lián)體傳感器信號處理器
文件頁數(shù): 17/28頁
文件大?。?/td> 496K
代理商: XRD9818
xr
XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
17
4.1.2
4.1.2.1
In CCD mode a clamp is required to level shift the CCD output signal into XRD9818’s input common mode
range. The clamp circuitry ensures that the signals present at the analog inputs fall within the operating range
of those pins. The clamp operation takes place while BSAMP is active. When BSAMP is active, SW1 is closed
connecting the C/R DAC to the analog input pin. This establishes the C/R DAC voltage on the external
coupling cap. When SW1 is opened, the C/R DAC voltage is stored on the external coupling cap. This clamping
operation will occur while BSAMP is active. The C/R DAC clamp voltage is programmable. This gives the
system designer added flexibility to make adjustments for different sensor signal swing and reset pulse
characteristics.
Clamp/Reference (C/R) DAC
Clamp Operation in CCD Mode
The XRD9818 has 2 clamp modes available for used in CCD applications, Line Clamp and Pixel Clamp.
Line Clamp mode only performs the clamp when the LCLMP pin is active. The control timing,
φ
CL
, for SW1 is
generated by the “ANDing” of the external timing signals LCLMP & BSAMP and is shown in Figure 6.
F
IGURE
5. CCD
MODE
I
NPUT
C
LAMP
(
ALL
THREE
CHANNELS
ARE
IDENTICAL
)
F
IGURE
6. L
INE
C
LAMP
M
ODE
T
IMING
φ
R
φ
R
φ
CL
C/R DAC
to PGA
CMN-
RED+
CL[2]
CL[1]
CL[0]
C1
C2
Clamp/Reference DAC
SW1
SW2
RED+
SW3
0.1uf
CCD
ouput
C
IN
C
REF
1nf
CCD
IN
ADCLK
BSAMP
VSAMP
φ
CL
LCLMP
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XRD9818ACG 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
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