FIGURE
參數(shù)資料
型號: XRD87L99AIQ
廠商: Exar Corporation
文件頁數(shù): 2/24頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 2MSPS 44PQFP
產品變化通告: Obsolescence Notification 15/Apr/2010
標準包裝: 160
位數(shù): 10
采樣率(每秒): 2M
數(shù)據(jù)接口: 并聯(lián)
功率耗散(最大): 450mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應商設備封裝: 44-PQFP(10x10)
包裝: 托盤
輸入數(shù)目和類型: *
xr
xr
XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
10
FIGURE 5. XRD87L99 COMPARATORS WITH CHANGING REFERENCE VOLTAGE
1.1
ACCURACY OF CONVERSION: DNL AND INL
The transfer function for an ideal A/D converter is
shown in Figure 6.
FIGURE 6. IDEAL A/D TRANSFER FUNCTION
The overflow transition (VOFW) takes place at:
VIN = VOFW = VREF(+)
The first and the last transitions for the data bits take
place at:
VIN = V001 = VREF(-) + 1.0 * LSB
VIN = V3FF = VREF(-) - 1.0 * LSB
VREF = VREF(+) - VREF(-)
LSB = VREF / 1024 = (V3FF - V001) / 1022
NOTE: The overflow transition is a flag and has no impact
on the data bits.
In a "real" converter the code-to-code transitions don't
fall exactly every VREF/1024 volts.
A positive DNL (Differential Non-Linearity) error
means that the real width of a particular code is larger
than 1 LSB. This error is measured in fractions of
LSBs.
A Max DNL specification guarantees that ALL code
widths (DNL errors) are within the stated value. A
specification of Max DNL = + 0.5 LSB means that all
code widths are within 0.5 and 1.5 LSB. If VREF = 2.56
V then 1 LSB = 2.5 mV and every code width is within
1.25 and 3.75 mV.
Settle by Clock Update Time
Reference Stable Time - For Sample A
IN1
Sample AIN1
Reference Stable Time - For Sample A
IN2
Hold Reference Value Past
Clock Change for t
AP Time
Short Cycle Sample will be discarded
Sample AIN2
AINX1
Not Used
A
INX0
Sample A
IN1
Sample A
IN2
Sample Ladder
for A
IN1
Sample Ladder
for A
INX1
Sample Ladder
for
AIN2
Sample Ladder
for A
INX2
Compare Ladder
V/S A
INX0
Compare Ladder
V/S A
IN1
Compare Ladder
V/S A
INX1
Compare Ladder
V/S A
IN2
DATA A
IN0
DATA A
INX0
DATA A
IN1
DATA A
INX1
Not Used
DATA
Ladder Compare
(LSB Bank)
Ladder Sample
Window (MSB Bank)
AIN Sample
Window
Clock
Update
References
External
Internal
External
t
S
ΦB
ΦS
ΦB
ΦS
A
INX1
3FF
3FE
3FD
V
REF(-)
V
REF(+)
DIGITAL
CODES
000
002
LSB
OFW=0
V
001
OFW=1
1 LSB
V001
V002
V
3FE
V
3FF
V
0FW =
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