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參數(shù)資料
| 型號： | XRD87L85SEVAL |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XRD87L85 |
| 產(chǎn)品變化通告： | Obsolescence Notification 15/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | * |
XRD87L85
6
Rev. 1.00
Figure 5. Equivalent Input Circuit
Figure 6. Typical Circuit Connections
APPLICATION NOTES
Signals should not exceed V
DD +0.5V or go below GND
–0.5V. All pins have internal protection diodes that will
protect them from short transients (<100
s) outside
the supply range.
AGND and DGND pins are connected internally
through the P-substrate. DC voltage differences be-
tween GND pins will cause undesirable internal sub-
strate currents.
The power supply (V
DD) and reference voltage (VRT &
V
RB) pins should be decoupled with 0.1F and 10F
capacitors to AGND, placed as close to the chip as
possible.
The digital outputs should not drive long wires or buses.
The capacitive coupling and reflections will contribute
noise to the conversion.
To avoid timing errors, use the rising edge of the sample
clock (CLK) to latch data from the XRD87L85 to other
parts of the system.
The reference can be biased internally by shorting V
RT
to V
RTS and VRB to VRBS. This will generate 0.4V at VRB
and 1.72V at V
RT (see Figure 5).
If the internal reference pins V
RTS and/or VRBS are not
used, they should be left unconnected.
The output enable pin (OE) should not be left uncon-
nected. If not controlled by an active signal, then it must
be tied to a logic low value.
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