Rev. 1.00 APPLICATION NOTES Signals should not exceed AV DD +0.5V or go below AGND -0" />
參數(shù)資料
型號: XRD87L75AIU
廠商: Exar Corporation
文件頁數(shù): 12/15頁
文件大?。?/td> 0K
描述: IC ADC 8BIT 10MSPS 20SSOP
產品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 66
位數(shù): 8
采樣率(每秒): 10M
數(shù)據接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 650mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 管件
輸入數(shù)目和類型: *
XRD87L75
6
Rev. 1.00
APPLICATION NOTES
Signals should not exceed AV
DD +0.5V or go below
AGND -0.5V or DV
DD +0.5V or DGND -0.5V. All pins
have internal protection diodes that will protect them
from short transients (<100
s) outside the supply
range.
AGND and DGND pins are connected internally through
the P- substrate. DC voltage differences between these
pins will cause undesirable internal substrate currents.
The power supply (AV
DD) and reference voltage (VRT &
V
RB) pins should be decoupled with 0.1F and 10F
capacitors to AGND, placed as close to the chip as
possible.
The digital outputs should not drive long wires or buses.
The capacitive coupling and reflections will contribute
noise to the conversion.
To avoid timing errors, use the rising edge of the sample
clock (CLK) to latch data from the XRD87L75 to other
parts of the system.
The reference can be biased internally by shorting V
RT
to V
RTS and VRB to VRBS. This will generate 0.4V at VRB
and 1.72V at V
RT (see Figure 5.).
If the internal reference pins V
RTS and/or VRBS are not
used they should be left unconnected.
Graph 1. DNL vs. Code
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0
32
64
96
128
160
192
224
256
Code
DNL
(LSB)
Vdd = 3.3V
Vrt = 2.5V
Vrb = 0.5V
Fs = 6MHz
Ta = 25
oC
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