REV. 1.0.0 2.9 Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Wri" />
參數(shù)資料
型號(hào)： XRA1403IG24-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 15/16頁(yè)
文件大?。?/td> 0K
描述： IC I/O EXPANDER SPI 16B 24TSSOP
標(biāo)準(zhǔn)包裝： 62
接口： SPI
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 26MHz
電源電壓： 1.65 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
其它名稱： 1016-1723-5
XRA1403
8
16-BIT SPI GPIO EXPANDER WITH RESET INPUT
REV. 1.0.0
2.9
Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Write
This register enables/disables the internal pull-up resistors for an input. Writing a ’1’ to these bits will enable
the internal pull-up resistors. Writing a ’0’ to these bits will disable the internal pull-up resistors. The MSB of
this register corresponds with P7 and the LSB of this register corresponds with P0.
2.10
Input Internal Pull-up Enable/Disable Register 2 (PUR2) - Read/Write
This register enables/disables the internal pull-up resistors for an input. Writing a ’1’ to these bits will enable
the internal pull-up resistors. Writing a ’0’ to these bits will disable the internal pull-up resistors. The MSB of
this register corresponds with P15 and the LSB of this register corresponds with P8.
2.11
Input Interrupt Enable Register 1 (IER1) - Read/Write
This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.
Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete
details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR
bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.
2.12
Input Interrupt Enable Register 2 (IER2) - Read/Write
This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.
Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete
details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR
bit is 0. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8.
2.13
Output Three-State Control Register 1 (TSCR1) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB
of this register corresponds with P0.
2.14
Output Three-State Control Register 2 (TSCR2) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P15 and the
LSB of this register corresponds with P8.
2.15
Input Interrupt Status Register 1 (ISR1) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of
this register corresponds with P0.
2.16
Input Interrupt Status Register 2 (ISR2) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of
this register corresponds with P8.
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