REV. 1.0.0 1.0 FUNCTIONAL DESCRIPTIONS 1.1 I2
參數(shù)資料
型號(hào): XRA1200PIL16-F
廠商: Exar Corporation
文件頁(yè)數(shù): 11/16頁(yè)
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16QFN
標(biāo)準(zhǔn)包裝: 490
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 散裝
其它名稱(chēng): 1016-1709
XRA1200/1200P
4
8-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA120x responds to each write with an acknowledge
(SDA driven LOW by XRA1200/1200P for one clock cycle when SCL is HIGH). The last byte sent by an I2C-
bus master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5
below. For complete details, see the I2C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
SW
A
AP
SL AVE
AD D R ESS
CO M M A ND
BYT E
DA T A
BYT E
W h ite b lock: h o st to X R A 1 20 x
G rey block: X R A 12 0 x to h ost
FIGURE 5. MASTER READS FROM SLAVE
SW
A
AR
SLAVE
ADDRESS
COMMAND
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
A
S
SLAVE
ADDRESS
nDATA
ANA
P
LAST DATA
2
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