參數(shù)資料
型號(hào): XR88C681J
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: CMOS DUAL CHANNEL UART (DUART)
中文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 39/99頁(yè)
文件大小: 1913K
代理商: XR88C681J
XR88C681
1
CPU
#7
#:
#7
#2#
#2
#:
#7
#2#
#2
#:
#7
#2#
#2
#:
#7
#2#
#2
#:
;
8#082
9B2
,##G
Figure 15. A Diagram of Numerous DUARTs Configured in an Interrupt
Daisy Chain (for Z-Mode Operation)
;
# $$((
% %% #2#$#2 (%L(' $+($
% +%4
#7 $
#: (%"
$
IEI - Interrupt Enable Input
(% '((- ( (% & ( (+
'+(-$
( $ #+ (% ( (%
-(' C(-D
%3$ ( E%%" +
(%" $
Note:
ThoseinterruptswhichhavebeenmaskedoutbytheIMRare
still disabled. However, if this input is at a logic “l(fā)ow”, then all
interrupts (whether masked or unmasked) are disabled.
Hence, IEI can act to globally disable all DUART interrupt
requests.
(%
IEO - Interrupt Enable Output
(% '((- (% & ( (+
'+(-$ ( $ (% (% +
(%''$ #2#( + ((&
$('
(%
'$((%
(%
(% C(-D (+
+
+(-
$('H% #2# ( (% -(' C(-D
$(' (% E%(- ( +
,
(" E%$ & $('" % M%
%('$
#+&+%'$((% +%" #2((
-(' CD
Note
:
Once the IEO pin has toggled “l(fā)ow”, and the CPU has ac-
knowledgedtheinterruptrequestandhascompletedtheinter-
ruptserviceroutine,theIEOpinwillremain“l(fā)ow”untiltheuser
invokesthe“RESETIUS”command(seeTable 3).Therefore,
if the DUART is going to operate inthe Z-Mode,the usermust
include the “RESET IUS” Command at the very end of the
DUART interrupt service routine.
System Level Application of the IEI and IEO pins
Figure 15
$('% %(% + % ''$ (
$(%&'( +%( # (% +(-" +%
% (-% ( ((& (% (% '% (%
H% #2# ( (% $($ ;'' +"
%3$ ( E%%" + (%
&% $
$('" '$ M%
(- + C(-% ( ((&D $(' (% +
(((& (%(%'% #2#(+(%
((& $(' (% ''$
(-% ((& B C(-% ((&D
$(' E%% (" (% #2 ( --
CD (% ( ( " $(% C ((&D $('
#2
+
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