參數(shù)資料
型號(hào): XR82C684
廠商: Exar Corporation
英文描述: CMOS QUAD CHANNEL UART (QUART)
中文描述: 的CMOS四通道UART(夸脫)
文件頁數(shù): 24/107頁
文件大?。?/td> 2244K
代理商: XR82C684
XR82C684
@
* 3(, ( # ( 3( % ,( *
; (% / 1
$*(%(*((%' *(, *'( % $ ;*
((' <<# (% (*( (% % 3 '' (%
%* *
;
%*'' '%%; ' * (%(
(% ' 3 + % ; $* '' (%
3((, ( '% ; (% *# (% ( 3( %
,(# * 3(,
( # 3 '' (%
( ;
3&
Note:
indicator, this bit will not be set (nor will produce an
interrupt request) if one or two characters are still
remaining in RHRC, following data reception. Hence, it is
possible that the last two characters in a string of data
(being received) could be lost due to this phenomenon.
Therefore, the user is advised to read RHRC until empty.
If this bit is configured to reflect the FFULLC
ISR2[0]: Channel C Transmitter Ready
(% ( (% (' * 8!H # PQ
(% (# 3 %# (('% ; (% & (%
& '' '' * +
' 3 + 3(% 3 '' ;F
(% % ,(# 3 '' (% %*
8!H (% % 3
(% ' 3 %( (% (%
'% ( ; 3(
(% 3( %(
( (%
%( (% (((&
%( (%
C.2 Interrupt Mask Registers (IMR1 and IMR2)
$ %6 ,(%%
,(%% 3(' % % %' ' (( %
3( '% (%% $ I%
'%% * # (* * $ (%
%%(&
% %
' %%# )( * $ $
% 3
' /E( &1
$
; 3# *
IMR1 Bit Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
L**
L
L**
L
L**
L
L**
L
L**
L
L**
L
L**
L
L**
L
IMR2 Bit Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
D
RXRDY/
FFULLD
TXRDY D
Counter
Ready
Delta Break
C
RXRDY/
FFULLC
TXRDYC
L**
L
L**
L
L**
L
L**
L
L**
L
L**
L
L**
L
L**
L
$* % 3(%%
% 3( /1 ( 3(( $# ' % (,
$ (( <(63(%# (% %6
'( ' (( '%(,
% 3( /1 ( '( ' % (,
' ((
'( (# -%
(#
%
Please note that the IMRs are Write Only Registers, and
can therefore not be read by the processor.
C.3 Masked Interrupt Status Register (MISR1 and
MISR2)
' * $ ,(% (% %('& %%
* :!(, $ $ ,
$ L P$ %Q
P$ %Q
((( * $ (' (%
& (, $%(% (%3(( $%'
,, /(,1
( ' % (, ' (( %
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