REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO RTSB# 15 22 G5 O UART channel B Request-to-Send (active low) or general" />
參數(shù)資料
型號(hào)： XR68M752IL32TR-F
廠商： Exar Corporation
文件頁數(shù)： 52/54頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 32QFN
標(biāo)準(zhǔn)包裝： 3,000
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
XR16M752/XR68M752
7
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
RTSB#
15
22
G5
O
UART channel B Request-to-Send (active low) or general
purpose output. This port must be asserted prior to using
auto RTS flow control, see EFR[6] and IER[6]. For auto
RS485 half-duplex direction control, see DLD[6].
CTSB#
16
23
F6
I
UART channel B Clear-to-Send (active low) or general
purpose input. It can be used for auto CTS flow control,
see EFR[7] and IER[7]. This input should be connected to
VCC or GND when not used.
DTRB#
-
35
C7
O
UART channel B Data-Terminal-Ready (active low) or
general purpose output. If it is not used, leave it uncon-
nected.
DSRB#
-
20
F5
I
UART channel B Data-Set-Ready (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
CDB#
-
16
F3
I
UART channel B Carrier-Detect (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
RIB#
-
21
E4
I
UART channel B Ring-Indicator (active low) or general
purpose input. This input should be connected to VCC or
GND when not used.
OP2B#
-
9
E3
O
Output Port 2 Channel B - The output state is defined by
the user and through the software setting of MCR[3].
INTB is set to the active mode and OP2B# output LOW
when MCR[3] is set to a logic 1. INTB is set to the three
state mode and OP2B# output HIGH when MCR[3] is set
to a logic 0. See MCR[3]. If INTB is used, this output
should not be used as a general output else it will disturb
the INTB output functionality.
ANCILLARY SIGNALS
XTAL1
10
13
G1
I
Crystal or external clock input.
XTAL2
11
14
G2
O
Crystal or buffered clock output.
PwrSave
-
F1
I
PowerSave (active high, internal pull-down resistor). This
feature isolates the 752’s data bus interface from the host
preventing other bus activities that cause higher power
drain during sleep mode. See Sleep Mode with Auto
Wake-up and PowerSave Feature section for details.
16/68#
17
24
G6
I
Intel or Motorola Bus Select (internal pull-up resistor).
This pin is not available for the XR16M752. This pin is
available for the XR68M752 only.
When 16/68# pin is HIGH, 16 or Intel Mode, the device
will operate in the Intel bus type of interface.
When 16/68# pin is LOW, 68 or Motorola mode, the
device will operate in the Motorola bus type of interface.
Pin Description
NAME
32-QFN
PIN #
48-TQFP
PIN #
49-STBGA
PIN #
TYPE
DESCRIPTION
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