REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ] TABLE
參數(shù)資料
型號(hào)： XR68M752IL32-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 22/54頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 64B DUAL 32QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 托盤
XR16M752/XR68M752
29
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
]
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xoff or Special character)
7
1
0
CTS#, RTS# change of state
-
0
1
None (default)
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is set when EFR[4] = 1 and IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of
the Xoff character(s). If this is an Xoff interrupt, it is cleared when XON is received. If it is a special character
interrupt, it is cleared by reading ISR.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR[4] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
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