- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16523 > XR68M752IL-0B-EB (Exar Corporation)EVAL BOARD FOR XR68M752 32QFN PDF資料下載
參數(shù)資料
| 型號： | XR68M752IL-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 27/54頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR68M752 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
XR16M752/XR68M752
33
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
MCR[2]: OP1# / FIFO Rdy Enable
OP1# is not available as an output pin on the M752. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the SPR, TLR and FIFO Rdy registers. All of these registers are
accessible at address offset 0x7 when LCR≠0xBF. However, LCR = 0xBF is required to access EFR.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X7
EFR[4] MCR[6] MCR[4, 2] Register at Address Offset 0x7
0
X
≠’01’
Scratchpad Register (SPR)
1
0
≠’01’
Scratchpad Register (SPR)
1
≠’01’
Trigger Level Register (TLR)
X
=’01’
FIFO Ready Register (FIFO Rdy)
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M752 is programmed to use the Xon/Xoff flow control.
MCR[6]: TCR and TLR Enable (requires EFR bit-4=1 to write to this bit)
This bit enables the TCR and TLR registers at address offset 0x6 and 0x7, respectively. See Table 12 above
for the correct register setting to access the TLR register. See Table 13 below for the setting to access the
TCR register.
Logic 0 = Reserved (default).
Logic 1 = Enable access to the TCR and TLR registers.
TABLE 13: REGISTER AT ADDRESS OFFSET 0X6
EFR[4] MCR[6] Register at Address Offset 0x6
0
X
Modem Status Register (MSR)
1
0
Modem Status Register (MSR)
1
Trigger Control Register (TCR)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LBR2518T101M | INDUCTOR WOUND 100UH 80MA 1007 |
| VE-JVY-EZ-S | CONVERTER MOD DC/DC 3.3V 16.5W |
| XR16V2752IL-0B-EB | EVAL BOARD FOR V2752 32QFN |
| EEU-FR1J271L | CAP ALUM 270UF 63V 20% RADIAL |
| UPA0J561MPD1TD | CAP ALUM 560UF 6.3V 20% RADIAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR68M752IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR68M752IL32-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR68M752IL32TR-F | 功能描述:UART 接口集成電路 W/64 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR68M752IM-0B-EB | 功能描述:界面開發(fā)工具 Support XR68M752 48L TQFP, PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR68M752IM48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。