REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.20 Internal Loopback The M752 UART provides an interna" />
參數(shù)資料
型號(hào)： XR68M752IB-0A-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 16/54頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR 68M752 49BGA
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M752/XR68M752
23
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.20
Internal Loopback
The M752 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem
/
G
en
eral
Purpos
e
Cont
rol
Logic
Inte
rn
a
lD
a
ta
Bus
L
ines
and
Co
ntrol
Signa
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
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