參數(shù)資料
型號(hào): XR68C92IP
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
中文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: PLASTIC, DIP-40
文件頁數(shù): 4/32頁
文件大小: 282K
代理商: XR68C92IP
XR68C92/192
4
Rev. P1.10
SYMBOL DESCRIPTION
(* 44 TQFP Package)
Symbol
Pin
40
Signal
type
Pin Description
44
44*
-
DTACK
10
9
4
O
Data transfer acknowledge (three-state active low output).
During Read, Write, or interrupt cycle goes low to indicate
proper transfer of data between the CPU and XR68C92/
192.
RX A/B
35,11
31,10
29,5
I
Serial data input. The serial information (data) received
from serial port to XR68C92/192 receive input circuit. A
mark (high) is logic one and a space (low) is logic zero.
TX A/B
33,13
30,11
28,6
O
Serial data output. The serial data is transmitted via this pin
with additional start , stop and parity bits. The TX will be held
in mark (high) state during reset, local loop back mode or
when the transmitter is disabled.
OP0
32
29
27
O
Multi-purpose output. General purpose output or Channel A
Request-To-Send (-RTSA active low).
OP1
14
12
7
O
Multi-purpose output. General purpose output or Channel B
Request-To-Send (-RTSB active low).
OP2
31
28
26
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bits 1,0:
TxAClk1
-Transmit 1X clock.
TxAClk16
-Transmit 16X clock
RxAClk1
-Receive 1X clock
OP3
15
13
8
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bits 3,2:
C/T
-Counter timer output (Open drain output)
TxBClk1
-Transmit 1X clock
RxBClk1
-Receive 1X clock
OP4
30
27
25
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bit 4:
-
RxARDY
-Receive ready signal (Open drain output)
-RxAFULL
- Receive FIFO full signal (Open drain output)
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參數(shù)描述
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