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參數資料
型號: XR21V1410IL16TR-F
廠商: Exar Corporation
文件頁數: 24/30頁
文件大小: 0K
描述: IC USB UART FIFO FULL SPD 16QFN
產品培訓模塊: XR21V141x Full-Speed USB UART Family
標準包裝: 3,000
特點: *
通道數: 1,UART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應商設備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
配用: 1016-1299-ND - EVAL BOARD FOR XR21V1410IL
30
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2014 EXAR Corporation
Datasheet January 2014.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XR21V1410
1-CH FULL-SPEED USB UART
REV. 1.4.0
REVISION HISTORY
DATE
REVISION
DESCRIPTION
June 2009
1.0.0
Released Datasheet
September 2010
1.1.0
Clarified pin functionality, wide mode and low latency mode including registers /
blocks, clarified FLOW_CONTROL and GPIO_MODE register functionality.
April 2011
1.2.0
Updated ordering information, SDA/SCL pin types, modified GPIO0 pin name and
added LOOPBACK_CTL register and description.
April 2012
1.3.0
Updated LOWPOWER pin description, bMaxPacketSize and DC electrical charac-
terisitics. See PCN12-0305-01 for more details.
July 2013
1.3.1
Updated package drawing QFN16
January 2014
1.4.0
Added Windows driver versions, added absolute maximum tables, added ESD pro-
tection ratings, added QFN package center pad to pin descriptions, minor clarifica-
tions including requirement for even Product ID in Windows OS. Updated package
drawing. [ECN: 1402-04]
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