REV. 1.0.0 3.9 Setup/Hysteresis Register (SHR) - Write Onl" />
參數(shù)資料
型號(hào): XR20M1280L40-0A-EB
廠商: Exar Corporation
文件頁(yè)數(shù): 35/63頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR XR20M1280L40
產(chǎn)品培訓(xùn)模塊: XR21V141x Full-Speed USB UART Family
UARTs with Integrated Level Shifters
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
已用 IC / 零件: XR20M1280L40
已供物品:
其它名稱: 1016-1628
XR20M1280
40
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
3.9
Setup/Hysteresis Register (SHR) - Write Only
In the Auto RS-485 half-duplex mode, the RTS# control output can be asserted from 0 to 15 bit times before
data is transmitted to allow for the startup time of an RS-485 transceiver that may be in shutdown mode. The
RTS# control output can also be delayed from 0 to 15 bit times after the last byte has been transmitted to allow
the data to propogate down long data cables.
In the Auto RTS flow control mode, this register selects the hysteresis levels that will be used with
programmable trigger levels (Trigger Table-D).
SHR[3:0]: RS-485 Turn-Around Delay / Auto RTS Hysteresis
When the Auto RS-485 half-duplex mode is enabled (FCTR[3] = 1), the value programmed in these bits will be
the number of bits (0-15) the RTS# pin will wait before it is de-asserted after the last byte that has been
transmitted.
When Auto RTS flow control is enabled (EFR[6] = 1) and programmable trigger levels are used (FCTR[5:4] =
’11’), these bits select the hysteresis levels for the RTS# flow control pin (See Table 15).
TABLE 15: AUTO RTS HYSTERESIS
SHR BIT-3
SHR BIT-2
SHR BIT-1
SHR BIT-0
RTS# HYSTERESIS
(CHARACTERS)
0
1
0
1
0
1
0
±4
±6
±8
0
1
0
1
0
1
0
1
±8
±16
±24
±32
1
0
1
0
1
0
1
±40
±44
±48
±52
1
0
1
0
1
0
1
±12
±20
±28
±36
SHR[7:4]: RS-485 Setup Delay
When the Auto RS-485 half-duplex mode is enabled (FCTR[3] = 1), the value programmed in these bits will be
the number of bits (0-15) the RTS# pin is asserted before the first byte is transmitted.
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