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參數(shù)資料
型號(hào)： XR20M1172L32-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 53/55頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR20M1172 32QFN
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR20M1172
主要屬性： 2 通道
次要屬性： I²C & SPI 接口
已供物品： 板
其它名稱： 1016-1625
XR20M1172L32-0B-EB-ND
XR20M1172
7
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
2.0
FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The M1172 can operate with either an I2C-bus interface or an SPI interface. The CPU interface is selected via
the I2C/SPI# input pin.
2.1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-
bus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial
clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to
400 kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW
when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The M1172 responds to each write with an
acknowledge (SDA driven LOW by M1172 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the
M1172 will respond with a negative acknowledge (SDA driven HIGH by M1172 for one clock cycle when SCL is
HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master is a stop bit (SDA
transition from LOW to HIGH when SCL is HIGH).
See Figures 3 - 5 below. For complete details, see the
I2C-bus specifications.
FIGURE 3. I2C START AND STOP CONDITIONS
FIGURE 4. MASTER WRITES TO SLAVE (M1172)
FIGURE 5. MASTER READS FROM SLAVE (M1172)
SDA
SCL
S
P
START condition
STOP condition
S
W
A
P
SLAVE
ADDRESS
REGISTER
ADDRESS
nDATA
White block: host to UART
Grey block: UART to host
S
W
A
R
SLAVE
ADDRESS
REGISTER
ADDRESS
White block: host to UART
Grey block: UART to host
A
S
SLAVE
ADDRESS
nDATA
A
NA
P
LAST DATA
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